535 lines
14 KiB
ArmAsm
535 lines
14 KiB
ArmAsm
/*
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* linux/arch/arm/mm/proc-xsc3.S
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*
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* Original Author: Matthew Gilbert
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* Current Maintainer: Lennert Buytenhek <buytenh@wantstofly.org>
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*
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* Copyright 2004 (C) Intel Corp.
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* Copyright 2005 (C) MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* MMU functions for the Intel XScale3 Core (XSC3). The XSC3 core is
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* an extension to Intel's original XScale core that adds the following
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* features:
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*
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* - ARMv6 Supersections
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* - Low Locality Reference pages (replaces mini-cache)
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* - 36-bit addressing
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* - L2 cache
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* - Cache coherency if chipset supports it
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*
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* Based on original XScale code by Nicolas Pitre.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include "proc-macros.S"
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/*
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* This is the maximum size of an area which will be flushed. If the
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* area is larger than this, then we flush the whole cache.
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*/
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#define MAX_AREA_SIZE 32768
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/*
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* The cache line size of the L1 I, L1 D and unified L2 cache.
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*/
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#define CACHELINESIZE 32
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/*
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* The size of the L1 D cache.
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*/
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#define CACHESIZE 32768
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/*
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* This macro is used to wait for a CP15 write and is needed when we
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* have to ensure that the last operation to the coprocessor was
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* completed before continuing with operation.
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*/
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.macro cpwait_ret, lr, rd
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mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
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sub pc, \lr, \rd, LSR #32 @ wait for completion and
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@ flush instruction pipeline
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.endm
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/*
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* This macro cleans and invalidates the entire L1 D cache.
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*/
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.macro clean_d_cache rd, rs
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mov \rd, #0x1f00
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orr \rd, \rd, #0x00e0
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1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
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adds \rd, \rd, #0x40000000
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bcc 1b
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subs \rd, \rd, #0x20
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bpl 1b
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.endm
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.text
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/*
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* cpu_xsc3_proc_init()
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*
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* Nothing too exciting at the moment
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*/
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ENTRY(cpu_xsc3_proc_init)
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mov pc, lr
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/*
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* cpu_xsc3_proc_fin()
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*/
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ENTRY(cpu_xsc3_proc_fin)
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1800 @ ...IZ...........
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bic r0, r0, #0x0006 @ .............CA.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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mov pc, lr
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/*
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* cpu_xsc3_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* loc: location to jump to for soft reset
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*/
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.align 5
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ENTRY(cpu_xsc3_reset)
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mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
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msr cpsr_c, r1 @ reset CPSR
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mrc p15, 0, r1, c1, c0, 0 @ ctrl register
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bic r1, r1, #0x3900 @ ..VIZ..S........
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bic r1, r1, #0x0086 @ ........B....CA.
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mcr p15, 0, r1, c1, c0, 0 @ ctrl register
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mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
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bic r1, r1, #0x0001 @ ...............M
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mcr p15, 0, r1, c1, c0, 0 @ ctrl register
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@ CAUTION: MMU turned off from this point. We count on the pipeline
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@ already containing those two last instructions to survive.
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
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mov pc, r0
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/*
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* cpu_xsc3_do_idle()
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*
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* Cause the processor to idle
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*
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* For now we do nothing but go to idle mode for every case
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*
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* XScale supports clock switching, but using idle mode support
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* allows external hardware to react to system state changes.
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*/
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.align 5
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ENTRY(cpu_xsc3_do_idle)
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mov r0, #1
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mcr p14, 0, r0, c7, c0, 0 @ go to idle
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mov pc, lr
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/* ================================= CACHE ================================ */
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/*
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* flush_icache_all()
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*
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* Unconditionally clean and invalidate the entire icache.
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*/
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ENTRY(xsc3_flush_icache_all)
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mov pc, lr
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ENDPROC(xsc3_flush_icache_all)
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/*
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* flush_user_cache_all()
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*
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* Invalidate all cache entries in a particular address
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* space.
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*/
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ENTRY(xsc3_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(xsc3_flush_kern_cache_all)
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mov r2, #VM_EXEC
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mov ip, #0
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__flush_whole_cache:
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clean_d_cache r0, r1
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
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mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
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mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
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mov pc, lr
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/*
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* flush_user_cache_range(start, end, vm_flags)
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*
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* Invalidate a range of cache entries in the specified
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* address space.
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*
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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* - vma - vma_area_struct describing address space
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*/
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.align 5
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ENTRY(xsc3_flush_user_cache_range)
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mov ip, #0
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sub r3, r1, r0 @ calculate total size
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cmp r3, #MAX_AREA_SIZE
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bhs __flush_whole_cache
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1: tst r2, #VM_EXEC
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
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mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
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mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
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mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
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mov pc, lr
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the I cache and the D cache in the
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* region described by start. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* Note: single I-cache line invalidation isn't used here since
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* it also trashes the mini I-cache used by JTAG debuggers.
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*/
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ENTRY(xsc3_coherent_kern_range)
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/* FALLTHROUGH */
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ENTRY(xsc3_coherent_user_range)
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bic r0, r0, #CACHELINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
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mcr p15, 0, r0, c7, c10, 4 @ data write barrier
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mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
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mov pc, lr
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/*
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* flush_kern_dcache_area(void *addr, size_t size)
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache.
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*
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* - addr - kernel address
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* - size - region size
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*/
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ENTRY(xsc3_flush_kern_dcache_area)
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add r1, r0, r1
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1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
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mcr p15, 0, r0, c7, c10, 4 @ data write barrier
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mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
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mov pc, lr
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/*
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* dma_inv_range(start, end)
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*
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* Invalidate (discard) the specified virtual address range.
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* May not write back any entries. If 'start' or 'end'
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* are not cache line aligned, those lines must be written
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* back.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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xsc3_dma_inv_range:
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tst r0, #CACHELINESIZE - 1
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bic r0, r0, #CACHELINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
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tst r1, #CACHELINESIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ clean L1 D line
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ data write barrier
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mov pc, lr
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/*
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* dma_clean_range(start, end)
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*
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* Clean the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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xsc3_dma_clean_range:
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bic r0, r0, #CACHELINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ data write barrier
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mov pc, lr
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/*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(xsc3_dma_flush_range)
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bic r0, r0, #CACHELINESIZE - 1
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1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ data write barrier
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mov pc, lr
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/*
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* dma_map_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(xsc3_dma_map_area)
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add r1, r1, r0
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cmp r2, #DMA_TO_DEVICE
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beq xsc3_dma_clean_range
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bcs xsc3_dma_inv_range
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b xsc3_dma_flush_range
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ENDPROC(xsc3_dma_map_area)
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/*
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* dma_unmap_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(xsc3_dma_unmap_area)
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mov pc, lr
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ENDPROC(xsc3_dma_unmap_area)
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@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
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define_cache_functions xsc3
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ENTRY(cpu_xsc3_dcache_clean_area)
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1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
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add r0, r0, #CACHELINESIZE
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subs r1, r1, #CACHELINESIZE
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bhi 1b
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mov pc, lr
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/* =============================== PageTable ============================== */
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/*
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* cpu_xsc3_switch_mm(pgd)
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*
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* Set the translation base pointer to be as described by pgd.
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*
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* pgd: new page tables
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*/
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.align 5
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ENTRY(cpu_xsc3_switch_mm)
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clean_d_cache r1, r2
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mcr p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
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mcr p15, 0, ip, c7, c10, 4 @ data write barrier
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mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
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orr r0, r0, #0x18 @ cache the page table in L2
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
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cpwait_ret lr, ip
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/*
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* cpu_xsc3_set_pte_ext(ptep, pte, ext)
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*
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* Set a PTE and flush it out
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*/
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cpu_xsc3_mt_table:
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.long 0x00 @ L_PTE_MT_UNCACHED
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.long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE
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.long PTE_EXT_TEX(5) | PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
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.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
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.long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
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.long 0x00 @ unused
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.long 0x00 @ L_PTE_MT_MINICACHE (not present)
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.long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC (not present?)
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.long 0x00 @ unused
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.long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC
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.long 0x00 @ unused
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.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
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.long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
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.long 0x00 @ unused
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.long 0x00 @ unused
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.long 0x00 @ unused
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.align 5
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ENTRY(cpu_xsc3_set_pte_ext)
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xscale_set_pte_ext_prologue
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tst r1, #L_PTE_SHARED @ shared?
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and r1, r1, #L_PTE_MT_MASK
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adr ip, cpu_xsc3_mt_table
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ldr ip, [ip, r1]
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orrne r2, r2, #PTE_EXT_COHERENT @ interlock: mask in coherent bit
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bic r2, r2, #0x0c @ clear old C,B bits
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orr r2, r2, ip
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xscale_set_pte_ext_epilogue
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mov pc, lr
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.ltorg
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.align
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.globl cpu_xsc3_suspend_size
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.equ cpu_xsc3_suspend_size, 4 * 8
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#ifdef CONFIG_PM_SLEEP
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ENTRY(cpu_xsc3_do_suspend)
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stmfd sp!, {r4 - r10, lr}
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mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
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mrc p15, 0, r5, c15, c1, 0 @ CP access reg
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mrc p15, 0, r6, c13, c0, 0 @ PID
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mrc p15, 0, r7, c3, c0, 0 @ domain ID
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mrc p15, 0, r8, c2, c0, 0 @ translation table base addr
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mrc p15, 0, r9, c1, c0, 1 @ auxiliary control reg
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mrc p15, 0, r10, c1, c0, 0 @ control reg
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bic r4, r4, #2 @ clear frequency change bit
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stmia r0, {r1, r4 - r10} @ store v:p offset + cp regs
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ldmia sp!, {r4 - r10, pc}
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ENDPROC(cpu_xsc3_do_suspend)
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ENTRY(cpu_xsc3_do_resume)
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ldmia r0, {r1, r4 - r10} @ load v:p offset + cp regs
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
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mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer
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mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode.
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mcr p15, 0, r5, c15, c1, 0 @ CP access reg
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mcr p15, 0, r6, c13, c0, 0 @ PID
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mcr p15, 0, r7, c3, c0, 0 @ domain ID
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mcr p15, 0, r8, c2, c0, 0 @ translation table base addr
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mcr p15, 0, r9, c1, c0, 1 @ auxiliary control reg
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@ temporarily map resume_turn_on_mmu into the page table,
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@ otherwise prefetch abort occurs after MMU is turned on
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mov r0, r10 @ control register
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mov r2, r8, lsr #14 @ get TTB0 base
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mov r2, r2, lsl #14
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ldr r3, =0x542e @ section flags
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b cpu_resume_mmu
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ENDPROC(cpu_xsc3_do_resume)
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#endif
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__CPUINIT
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.type __xsc3_setup, #function
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__xsc3_setup:
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mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
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msr cpsr_c, r0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
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mcr p15, 0, ip, c7, c10, 4 @ data write barrier
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mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
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orr r4, r4, #0x18 @ cache the page table in L2
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mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
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mov r0, #1 << 6 @ cp6 access for early sched_clock
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mcr p15, 0, r0, c15, c1, 0 @ write CP access register
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mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg
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and r0, r0, #2 @ preserve bit P bit setting
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orr r0, r0, #(1 << 10) @ enable L2 for LLR cache
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mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
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adr r5, xsc3_crval
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ldmia r5, {r5, r6}
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#ifdef CONFIG_CACHE_XSC3L2
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mrc p15, 1, r0, c0, c0, 1 @ get L2 present information
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ands r0, r0, #0xf8
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orrne r6, r6, #(1 << 26) @ enable L2 if present
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#endif
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mrc p15, 0, r0, c1, c0, 0 @ get control register
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bic r0, r0, r5 @ ..V. ..R. .... ..A.
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orr r0, r0, r6 @ ..VI Z..S .... .C.M (mmu)
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@ ...I Z..S .... .... (uc)
|
|
mov pc, lr
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|
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.size __xsc3_setup, . - __xsc3_setup
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|
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.type xsc3_crval, #object
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xsc3_crval:
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crval clear=0x04002202, mmuset=0x00003905, ucset=0x00001900
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|
|
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__INITDATA
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@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
|
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define_processor_functions xsc3, dabort=v5t_early_abort, pabort=legacy_pabort, suspend=1
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|
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.section ".rodata"
|
|
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string cpu_arch_name, "armv5te"
|
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string cpu_elf_name, "v5"
|
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string cpu_xsc3_name, "XScale-V3 based processor"
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|
|
|
.align
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|
|
|
.section ".proc.info.init", #alloc, #execinstr
|
|
|
|
.macro xsc3_proc_info name:req, cpu_val:req, cpu_mask:req
|
|
.type __\name\()_proc_info,#object
|
|
__\name\()_proc_info:
|
|
.long \cpu_val
|
|
.long \cpu_mask
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_SECT_BUFFERABLE | \
|
|
PMD_SECT_CACHEABLE | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
b __xsc3_setup
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
|
.long cpu_xsc3_name
|
|
.long xsc3_processor_functions
|
|
.long v4wbi_tlb_fns
|
|
.long xsc3_mc_user_fns
|
|
.long xsc3_cache_fns
|
|
.size __\name\()_proc_info, . - __\name\()_proc_info
|
|
.endm
|
|
|
|
xsc3_proc_info xsc3, 0x69056000, 0xffffe000
|
|
|
|
/* Note: PXA935 changed its implementor ID from Intel to Marvell */
|
|
xsc3_proc_info xsc3_pxa935, 0x56056000, 0xffffe000
|