63 lines
1.9 KiB
C
63 lines
1.9 KiB
C
#ifndef __PLAT_GPIO_H
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#define __PLAT_GPIO_H
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/*
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* We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
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* one set of registers. The register offsets are organized below:
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*
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* GPLR GPDR GPSR GPCR GRER GFER GEDR
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* BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
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* BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
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* BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
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*
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* BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
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* BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
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* BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
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*
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* NOTE:
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* BANK 3 is only available on PXA27x and later processors.
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* BANK 4 and 5 are only available on PXA935
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*/
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#define GPIO_BANK(n) (GPIO_REGS_VIRT + BANK_OFF(n))
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#define GPLR_OFFSET 0x00
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#define GPDR_OFFSET 0x0C
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#define GPSR_OFFSET 0x18
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#define GPCR_OFFSET 0x24
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#define GRER_OFFSET 0x30
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#define GFER_OFFSET 0x3C
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#define GEDR_OFFSET 0x48
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static inline int gpio_get_value(unsigned gpio)
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{
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if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO))
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return GPLR(gpio) & GPIO_bit(gpio);
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else
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return __gpio_get_value(gpio);
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}
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static inline void gpio_set_value(unsigned gpio, int value)
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{
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if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) {
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if (value)
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GPSR(gpio) = GPIO_bit(gpio);
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else
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GPCR(gpio) = GPIO_bit(gpio);
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} else
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__gpio_set_value(gpio, value);
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}
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#define gpio_cansleep __gpio_cansleep
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/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
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* Those cases currently cause holes in the GPIO number space, the
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* actual number of the last GPIO is recorded by 'pxa_last_gpio'.
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*/
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extern int pxa_last_gpio;
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typedef int (*set_wake_t)(unsigned int irq, unsigned int on);
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extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn);
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#endif /* __PLAT_GPIO_H */
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