1144 lines
28 KiB
C
1144 lines
28 KiB
C
/*
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* Copyright (C) 1995 Linus Torvalds
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*/
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/*
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* This file handles the architecture-dependent parts of initialization
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*/
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/stddef.h>
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#include <linux/unistd.h>
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#include <linux/ptrace.h>
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#include <linux/slab.h>
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#include <linux/user.h>
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#include <linux/screen_info.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/initrd.h>
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#include <linux/highmem.h>
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#include <linux/bootmem.h>
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#include <linux/module.h>
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#include <asm/processor.h>
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#include <linux/console.h>
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#include <linux/seq_file.h>
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#include <linux/crash_dump.h>
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#include <linux/root_dev.h>
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#include <linux/pci.h>
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#include <linux/efi.h>
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#include <linux/acpi.h>
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#include <linux/kallsyms.h>
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#include <linux/edd.h>
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#include <linux/mmzone.h>
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#include <linux/kexec.h>
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#include <linux/cpufreq.h>
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#include <linux/dmi.h>
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#include <linux/dma-mapping.h>
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#include <linux/ctype.h>
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#include <linux/uaccess.h>
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#include <linux/init_ohci1394_dma.h>
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#include <asm/mtrr.h>
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#include <asm/uaccess.h>
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#include <asm/system.h>
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#include <asm/vsyscall.h>
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#include <asm/io.h>
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#include <asm/smp.h>
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#include <asm/msr.h>
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#include <asm/desc.h>
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#include <video/edid.h>
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#include <asm/e820.h>
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#include <asm/dma.h>
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#include <asm/gart.h>
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#include <asm/mpspec.h>
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#include <asm/mmu_context.h>
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#include <asm/proto.h>
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#include <asm/setup.h>
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#include <asm/numa.h>
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#include <asm/sections.h>
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#include <asm/dmi.h>
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#include <asm/cacheflush.h>
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#include <asm/mce.h>
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#include <asm/ds.h>
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#include <asm/topology.h>
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#include <asm/trampoline.h>
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#include <mach_apic.h>
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define ARCH_SETUP
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#endif
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/*
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* Machine setup..
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*/
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struct cpuinfo_x86 boot_cpu_data __read_mostly;
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EXPORT_SYMBOL(boot_cpu_data);
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__u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
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unsigned long mmu_cr4_features;
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/* Boot loader ID as an integer, for the benefit of proc_dointvec */
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int bootloader_type;
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unsigned long saved_video_mode;
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int force_mwait __cpuinitdata;
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/*
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* Early DMI memory
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*/
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int dmi_alloc_index;
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char dmi_alloc_data[DMI_MAX_DATA];
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/*
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* Setup options
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*/
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struct screen_info screen_info;
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EXPORT_SYMBOL(screen_info);
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struct sys_desc_table_struct {
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unsigned short length;
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unsigned char table[0];
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};
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struct edid_info edid_info;
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EXPORT_SYMBOL_GPL(edid_info);
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extern int root_mountflags;
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char __initdata command_line[COMMAND_LINE_SIZE];
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struct resource standard_io_resources[] = {
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{ .name = "dma1", .start = 0x00, .end = 0x1f,
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.flags = IORESOURCE_BUSY | IORESOURCE_IO },
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{ .name = "pic1", .start = 0x20, .end = 0x21,
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.flags = IORESOURCE_BUSY | IORESOURCE_IO },
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{ .name = "timer0", .start = 0x40, .end = 0x43,
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.flags = IORESOURCE_BUSY | IORESOURCE_IO },
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{ .name = "timer1", .start = 0x50, .end = 0x53,
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.flags = IORESOURCE_BUSY | IORESOURCE_IO },
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{ .name = "keyboard", .start = 0x60, .end = 0x6f,
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.flags = IORESOURCE_BUSY | IORESOURCE_IO },
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{ .name = "dma page reg", .start = 0x80, .end = 0x8f,
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.flags = IORESOURCE_BUSY | IORESOURCE_IO },
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{ .name = "pic2", .start = 0xa0, .end = 0xa1,
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.flags = IORESOURCE_BUSY | IORESOURCE_IO },
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{ .name = "dma2", .start = 0xc0, .end = 0xdf,
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.flags = IORESOURCE_BUSY | IORESOURCE_IO },
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{ .name = "fpu", .start = 0xf0, .end = 0xff,
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.flags = IORESOURCE_BUSY | IORESOURCE_IO }
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};
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#define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
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static struct resource data_resource = {
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.name = "Kernel data",
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.start = 0,
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.end = 0,
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.flags = IORESOURCE_RAM,
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};
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static struct resource code_resource = {
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.name = "Kernel code",
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.start = 0,
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.end = 0,
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.flags = IORESOURCE_RAM,
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};
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static struct resource bss_resource = {
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.name = "Kernel bss",
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.start = 0,
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.end = 0,
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.flags = IORESOURCE_RAM,
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};
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static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
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#ifdef CONFIG_PROC_VMCORE
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/* elfcorehdr= specifies the location of elf core header
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* stored by the crashed kernel. This option will be passed
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* by kexec loader to the capture kernel.
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*/
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static int __init setup_elfcorehdr(char *arg)
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{
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char *end;
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if (!arg)
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return -EINVAL;
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elfcorehdr_addr = memparse(arg, &end);
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return end > arg ? 0 : -EINVAL;
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}
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early_param("elfcorehdr", setup_elfcorehdr);
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#endif
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#ifndef CONFIG_NUMA
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static void __init
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contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
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{
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unsigned long bootmap_size, bootmap;
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bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
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bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size,
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PAGE_SIZE);
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if (bootmap == -1L)
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panic("Cannot find bootmem map of size %ld\n", bootmap_size);
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bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
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e820_register_active_regions(0, start_pfn, end_pfn);
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free_bootmem_with_active_regions(0, end_pfn);
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reserve_bootmem(bootmap, bootmap_size, BOOTMEM_DEFAULT);
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}
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#endif
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#if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
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struct edd edd;
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#ifdef CONFIG_EDD_MODULE
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EXPORT_SYMBOL(edd);
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#endif
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/**
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* copy_edd() - Copy the BIOS EDD information
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* from boot_params into a safe place.
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*
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*/
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static inline void copy_edd(void)
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{
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memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
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sizeof(edd.mbr_signature));
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memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
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edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
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edd.edd_info_nr = boot_params.eddbuf_entries;
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}
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#else
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static inline void copy_edd(void)
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{
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}
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#endif
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#ifdef CONFIG_KEXEC
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static void __init reserve_crashkernel(void)
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{
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unsigned long long total_mem;
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unsigned long long crash_size, crash_base;
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int ret;
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total_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
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ret = parse_crashkernel(boot_command_line, total_mem,
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&crash_size, &crash_base);
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if (ret == 0 && crash_size) {
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if (crash_base <= 0) {
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printk(KERN_INFO "crashkernel reservation failed - "
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"you have to specify a base address\n");
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return;
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}
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if (reserve_bootmem(crash_base, crash_size,
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BOOTMEM_EXCLUSIVE) < 0) {
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printk(KERN_INFO "crashkernel reservation failed - "
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"memory is in use\n");
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return;
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}
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printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
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"for crashkernel (System RAM: %ldMB)\n",
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(unsigned long)(crash_size >> 20),
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(unsigned long)(crash_base >> 20),
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(unsigned long)(total_mem >> 20));
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crashk_res.start = crash_base;
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crashk_res.end = crash_base + crash_size - 1;
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insert_resource(&iomem_resource, &crashk_res);
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}
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}
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#else
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static inline void __init reserve_crashkernel(void)
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{}
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#endif
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/* Overridden in paravirt.c if CONFIG_PARAVIRT */
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void __attribute__((weak)) __init memory_setup(void)
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{
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machine_specific_memory_setup();
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}
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/*
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* setup_arch - architecture-specific boot-time initializations
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*
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* Note: On x86_64, fixmaps are ready for use even before this is called.
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*/
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void __init setup_arch(char **cmdline_p)
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{
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unsigned i;
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printk(KERN_INFO "Command line: %s\n", boot_command_line);
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ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
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screen_info = boot_params.screen_info;
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edid_info = boot_params.edid_info;
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saved_video_mode = boot_params.hdr.vid_mode;
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bootloader_type = boot_params.hdr.type_of_loader;
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#ifdef CONFIG_BLK_DEV_RAM
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rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
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rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
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rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
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#endif
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#ifdef CONFIG_EFI
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if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
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"EL64", 4))
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efi_enabled = 1;
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#endif
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ARCH_SETUP
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memory_setup();
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copy_edd();
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if (!boot_params.hdr.root_flags)
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root_mountflags &= ~MS_RDONLY;
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init_mm.start_code = (unsigned long) &_text;
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init_mm.end_code = (unsigned long) &_etext;
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init_mm.end_data = (unsigned long) &_edata;
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init_mm.brk = (unsigned long) &_end;
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code_resource.start = virt_to_phys(&_text);
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code_resource.end = virt_to_phys(&_etext)-1;
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data_resource.start = virt_to_phys(&_etext);
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data_resource.end = virt_to_phys(&_edata)-1;
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bss_resource.start = virt_to_phys(&__bss_start);
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bss_resource.end = virt_to_phys(&__bss_stop)-1;
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early_identify_cpu(&boot_cpu_data);
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strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
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*cmdline_p = command_line;
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parse_early_param();
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#ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
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if (init_ohci1394_dma_early)
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init_ohci1394_dma_on_all_controllers();
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#endif
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finish_e820_parsing();
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/* after parse_early_param, so could debug it */
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insert_resource(&iomem_resource, &code_resource);
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insert_resource(&iomem_resource, &data_resource);
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insert_resource(&iomem_resource, &bss_resource);
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early_gart_iommu_check();
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e820_register_active_regions(0, 0, -1UL);
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/*
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* partially used pages are not usable - thus
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* we are rounding upwards:
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*/
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end_pfn = e820_end_of_ram();
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/* update e820 for memory not covered by WB MTRRs */
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mtrr_bp_init();
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if (mtrr_trim_uncached_memory(end_pfn)) {
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e820_register_active_regions(0, 0, -1UL);
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end_pfn = e820_end_of_ram();
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}
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num_physpages = end_pfn;
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check_efer();
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max_pfn_mapped = init_memory_mapping(0, (max_pfn_mapped << PAGE_SHIFT));
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if (efi_enabled)
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efi_init();
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vsmp_init();
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dmi_scan_machine();
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io_delay_init();
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#ifdef CONFIG_SMP
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/* setup to use the early static init tables during kernel startup */
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x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init;
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x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init;
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#ifdef CONFIG_NUMA
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x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init;
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#endif
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#endif
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#ifdef CONFIG_ACPI
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/*
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* Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
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* Call this early for SRAT node setup.
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*/
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acpi_boot_table_init();
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#endif
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/* How many end-of-memory variables you have, grandma! */
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max_low_pfn = end_pfn;
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max_pfn = end_pfn;
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high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
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/* Remove active ranges so rediscovery with NUMA-awareness happens */
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remove_all_active_ranges();
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#ifdef CONFIG_ACPI_NUMA
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/*
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* Parse SRAT to discover nodes.
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*/
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acpi_numa_init();
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#endif
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#ifdef CONFIG_NUMA
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numa_initmem_init(0, end_pfn);
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#else
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contig_initmem_init(0, end_pfn);
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#endif
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early_res_to_bootmem();
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dma32_reserve_bootmem();
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#ifdef CONFIG_ACPI_SLEEP
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/*
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* Reserve low memory region for sleep support.
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*/
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acpi_reserve_bootmem();
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#endif
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if (efi_enabled)
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efi_reserve_bootmem();
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/*
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* Find and reserve possible boot-time SMP configuration:
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*/
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find_smp_config();
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#ifdef CONFIG_BLK_DEV_INITRD
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if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
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unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
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unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
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unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
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unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
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if (ramdisk_end <= end_of_mem) {
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/*
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* don't need to reserve again, already reserved early
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* in x86_64_start_kernel, and early_res_to_bootmem
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* convert that to reserved in bootmem
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*/
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initrd_start = ramdisk_image + PAGE_OFFSET;
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initrd_end = initrd_start+ramdisk_size;
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} else {
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free_bootmem(ramdisk_image, ramdisk_size);
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printk(KERN_ERR "initrd extends beyond end of memory "
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"(0x%08lx > 0x%08lx)\ndisabling initrd\n",
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ramdisk_end, end_of_mem);
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initrd_start = 0;
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}
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}
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#endif
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reserve_crashkernel();
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paging_init();
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map_vsyscall();
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early_quirks();
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#ifdef CONFIG_ACPI
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/*
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* Read APIC and some other early information from ACPI tables.
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*/
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acpi_boot_init();
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#endif
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init_cpu_to_node();
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/*
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* get boot-time SMP configuration:
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*/
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if (smp_found_config)
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get_smp_config();
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init_apic_mappings();
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ioapic_init_mappings();
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/*
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* We trust e820 completely. No explicit ROM probing in memory.
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*/
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e820_reserve_resources();
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e820_mark_nosave_regions();
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/* request I/O space for devices used on all i[345]86 PCs */
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for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
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request_resource(&ioport_resource, &standard_io_resources[i]);
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e820_setup_gap();
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#ifdef CONFIG_VT
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#if defined(CONFIG_VGA_CONSOLE)
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if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
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conswitchp = &vga_con;
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#elif defined(CONFIG_DUMMY_CONSOLE)
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conswitchp = &dummy_con;
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#endif
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#endif
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}
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static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
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{
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unsigned int *v;
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if (c->extended_cpuid_level < 0x80000004)
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return 0;
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v = (unsigned int *) c->x86_model_id;
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cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
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cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
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cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
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c->x86_model_id[48] = 0;
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return 1;
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}
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|
|
static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
|
|
{
|
|
unsigned int n, dummy, eax, ebx, ecx, edx;
|
|
|
|
n = c->extended_cpuid_level;
|
|
|
|
if (n >= 0x80000005) {
|
|
cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
|
|
printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
|
|
"D cache %dK (%d bytes/line)\n",
|
|
edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
|
|
c->x86_cache_size = (ecx>>24) + (edx>>24);
|
|
/* On K8 L1 TLB is inclusive, so don't count it */
|
|
c->x86_tlbsize = 0;
|
|
}
|
|
|
|
if (n >= 0x80000006) {
|
|
cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
|
|
ecx = cpuid_ecx(0x80000006);
|
|
c->x86_cache_size = ecx >> 16;
|
|
c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
|
|
|
|
printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
|
|
c->x86_cache_size, ecx & 0xFF);
|
|
}
|
|
if (n >= 0x80000008) {
|
|
cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
|
|
c->x86_virt_bits = (eax >> 8) & 0xff;
|
|
c->x86_phys_bits = eax & 0xff;
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_NUMA
|
|
static int __cpuinit nearby_node(int apicid)
|
|
{
|
|
int i, node;
|
|
|
|
for (i = apicid - 1; i >= 0; i--) {
|
|
node = apicid_to_node[i];
|
|
if (node != NUMA_NO_NODE && node_online(node))
|
|
return node;
|
|
}
|
|
for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
|
|
node = apicid_to_node[i];
|
|
if (node != NUMA_NO_NODE && node_online(node))
|
|
return node;
|
|
}
|
|
return first_node(node_online_map); /* Shouldn't happen */
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* On a AMD dual core setup the lower bits of the APIC id distingush the cores.
|
|
* Assumes number of cores is a power of two.
|
|
*/
|
|
static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
|
|
{
|
|
#ifdef CONFIG_SMP
|
|
unsigned bits;
|
|
#ifdef CONFIG_NUMA
|
|
int cpu = smp_processor_id();
|
|
int node = 0;
|
|
unsigned apicid = hard_smp_processor_id();
|
|
#endif
|
|
bits = c->x86_coreid_bits;
|
|
|
|
/* Low order bits define the core id (index of core in socket) */
|
|
c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
|
|
/* Convert the initial APIC ID into the socket ID */
|
|
c->phys_proc_id = c->initial_apicid >> bits;
|
|
|
|
#ifdef CONFIG_NUMA
|
|
node = c->phys_proc_id;
|
|
if (apicid_to_node[apicid] != NUMA_NO_NODE)
|
|
node = apicid_to_node[apicid];
|
|
if (!node_online(node)) {
|
|
/* Two possibilities here:
|
|
- The CPU is missing memory and no node was created.
|
|
In that case try picking one from a nearby CPU
|
|
- The APIC IDs differ from the HyperTransport node IDs
|
|
which the K8 northbridge parsing fills in.
|
|
Assume they are all increased by a constant offset,
|
|
but in the same order as the HT nodeids.
|
|
If that doesn't result in a usable node fall back to the
|
|
path for the previous case. */
|
|
|
|
int ht_nodeid = c->initial_apicid;
|
|
|
|
if (ht_nodeid >= 0 &&
|
|
apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
|
|
node = apicid_to_node[ht_nodeid];
|
|
/* Pick a nearby node */
|
|
if (!node_online(node))
|
|
node = nearby_node(apicid);
|
|
}
|
|
numa_set_node(cpu, node);
|
|
|
|
printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
|
|
#endif
|
|
#endif
|
|
}
|
|
|
|
static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
|
|
{
|
|
#ifdef CONFIG_SMP
|
|
unsigned bits, ecx;
|
|
|
|
/* Multi core CPU? */
|
|
if (c->extended_cpuid_level < 0x80000008)
|
|
return;
|
|
|
|
ecx = cpuid_ecx(0x80000008);
|
|
|
|
c->x86_max_cores = (ecx & 0xff) + 1;
|
|
|
|
/* CPU telling us the core id bits shift? */
|
|
bits = (ecx >> 12) & 0xF;
|
|
|
|
/* Otherwise recompute */
|
|
if (bits == 0) {
|
|
while ((1 << bits) < c->x86_max_cores)
|
|
bits++;
|
|
}
|
|
|
|
c->x86_coreid_bits = bits;
|
|
|
|
#endif
|
|
}
|
|
|
|
#define ENABLE_C1E_MASK 0x18000000
|
|
#define CPUID_PROCESSOR_SIGNATURE 1
|
|
#define CPUID_XFAM 0x0ff00000
|
|
#define CPUID_XFAM_K8 0x00000000
|
|
#define CPUID_XFAM_10H 0x00100000
|
|
#define CPUID_XFAM_11H 0x00200000
|
|
#define CPUID_XMOD 0x000f0000
|
|
#define CPUID_XMOD_REV_F 0x00040000
|
|
|
|
/* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
|
|
static __cpuinit int amd_apic_timer_broken(void)
|
|
{
|
|
u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
|
|
|
|
switch (eax & CPUID_XFAM) {
|
|
case CPUID_XFAM_K8:
|
|
if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
|
|
break;
|
|
case CPUID_XFAM_10H:
|
|
case CPUID_XFAM_11H:
|
|
rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
|
|
if (lo & ENABLE_C1E_MASK)
|
|
return 1;
|
|
break;
|
|
default:
|
|
/* err on the side of caution */
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
|
|
{
|
|
early_init_amd_mc(c);
|
|
|
|
/* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
|
|
if (c->x86_power & (1<<8))
|
|
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
|
|
}
|
|
|
|
static void __cpuinit init_amd(struct cpuinfo_x86 *c)
|
|
{
|
|
unsigned level;
|
|
|
|
#ifdef CONFIG_SMP
|
|
unsigned long value;
|
|
|
|
/*
|
|
* Disable TLB flush filter by setting HWCR.FFDIS on K8
|
|
* bit 6 of msr C001_0015
|
|
*
|
|
* Errata 63 for SH-B3 steppings
|
|
* Errata 122 for all steppings (F+ have it disabled by default)
|
|
*/
|
|
if (c->x86 == 15) {
|
|
rdmsrl(MSR_K8_HWCR, value);
|
|
value |= 1 << 6;
|
|
wrmsrl(MSR_K8_HWCR, value);
|
|
}
|
|
#endif
|
|
|
|
/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
|
|
3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
|
|
clear_cpu_cap(c, 0*32+31);
|
|
|
|
/* On C+ stepping K8 rep microcode works well for copy/memset */
|
|
level = cpuid_eax(1);
|
|
if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
|
|
level >= 0x0f58))
|
|
set_cpu_cap(c, X86_FEATURE_REP_GOOD);
|
|
if (c->x86 == 0x10 || c->x86 == 0x11)
|
|
set_cpu_cap(c, X86_FEATURE_REP_GOOD);
|
|
|
|
/* Enable workaround for FXSAVE leak */
|
|
if (c->x86 >= 6)
|
|
set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
|
|
|
|
level = get_model_name(c);
|
|
if (!level) {
|
|
switch (c->x86) {
|
|
case 15:
|
|
/* Should distinguish Models here, but this is only
|
|
a fallback anyways. */
|
|
strcpy(c->x86_model_id, "Hammer");
|
|
break;
|
|
}
|
|
}
|
|
display_cacheinfo(c);
|
|
|
|
/* Multi core CPU? */
|
|
if (c->extended_cpuid_level >= 0x80000008)
|
|
amd_detect_cmp(c);
|
|
|
|
if (c->extended_cpuid_level >= 0x80000006 &&
|
|
(cpuid_edx(0x80000006) & 0xf000))
|
|
num_cache_leaves = 4;
|
|
else
|
|
num_cache_leaves = 3;
|
|
|
|
if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
|
|
set_cpu_cap(c, X86_FEATURE_K8);
|
|
|
|
/* MFENCE stops RDTSC speculation */
|
|
set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
|
|
|
|
if (amd_apic_timer_broken())
|
|
disable_apic_timer = 1;
|
|
|
|
if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
|
|
unsigned long long tseg;
|
|
|
|
/*
|
|
* Split up direct mapping around the TSEG SMM area.
|
|
* Don't do it for gbpages because there seems very little
|
|
* benefit in doing so.
|
|
*/
|
|
if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg) &&
|
|
(tseg >> PMD_SHIFT) < (max_pfn_mapped >> (PMD_SHIFT-PAGE_SHIFT)))
|
|
set_memory_4k((unsigned long)__va(tseg), 1);
|
|
}
|
|
}
|
|
|
|
void __cpuinit detect_ht(struct cpuinfo_x86 *c)
|
|
{
|
|
#ifdef CONFIG_SMP
|
|
u32 eax, ebx, ecx, edx;
|
|
int index_msb, core_bits;
|
|
|
|
cpuid(1, &eax, &ebx, &ecx, &edx);
|
|
|
|
|
|
if (!cpu_has(c, X86_FEATURE_HT))
|
|
return;
|
|
if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
|
|
goto out;
|
|
|
|
smp_num_siblings = (ebx & 0xff0000) >> 16;
|
|
|
|
if (smp_num_siblings == 1) {
|
|
printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
|
|
} else if (smp_num_siblings > 1) {
|
|
|
|
if (smp_num_siblings > NR_CPUS) {
|
|
printk(KERN_WARNING "CPU: Unsupported number of "
|
|
"siblings %d", smp_num_siblings);
|
|
smp_num_siblings = 1;
|
|
return;
|
|
}
|
|
|
|
index_msb = get_count_order(smp_num_siblings);
|
|
c->phys_proc_id = phys_pkg_id(index_msb);
|
|
|
|
smp_num_siblings = smp_num_siblings / c->x86_max_cores;
|
|
|
|
index_msb = get_count_order(smp_num_siblings);
|
|
|
|
core_bits = get_count_order(c->x86_max_cores);
|
|
|
|
c->cpu_core_id = phys_pkg_id(index_msb) &
|
|
((1 << core_bits) - 1);
|
|
}
|
|
out:
|
|
if ((c->x86_max_cores * smp_num_siblings) > 1) {
|
|
printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
|
|
c->phys_proc_id);
|
|
printk(KERN_INFO "CPU: Processor Core ID: %d\n",
|
|
c->cpu_core_id);
|
|
}
|
|
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* find out the number of processor cores on the die
|
|
*/
|
|
static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
|
|
{
|
|
unsigned int eax, t;
|
|
|
|
if (c->cpuid_level < 4)
|
|
return 1;
|
|
|
|
cpuid_count(4, 0, &eax, &t, &t, &t);
|
|
|
|
if (eax & 0x1f)
|
|
return ((eax >> 26) + 1);
|
|
else
|
|
return 1;
|
|
}
|
|
|
|
static void __cpuinit srat_detect_node(void)
|
|
{
|
|
#ifdef CONFIG_NUMA
|
|
unsigned node;
|
|
int cpu = smp_processor_id();
|
|
int apicid = hard_smp_processor_id();
|
|
|
|
/* Don't do the funky fallback heuristics the AMD version employs
|
|
for now. */
|
|
node = apicid_to_node[apicid];
|
|
if (node == NUMA_NO_NODE || !node_online(node))
|
|
node = first_node(node_online_map);
|
|
numa_set_node(cpu, node);
|
|
|
|
printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
|
|
#endif
|
|
}
|
|
|
|
static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
|
|
{
|
|
if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
|
|
(c->x86 == 0x6 && c->x86_model >= 0x0e))
|
|
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
|
|
}
|
|
|
|
static void __cpuinit init_intel(struct cpuinfo_x86 *c)
|
|
{
|
|
/* Cache sizes */
|
|
unsigned n;
|
|
|
|
init_intel_cacheinfo(c);
|
|
if (c->cpuid_level > 9) {
|
|
unsigned eax = cpuid_eax(10);
|
|
/* Check for version and the number of counters */
|
|
if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
|
|
set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
|
|
}
|
|
|
|
if (cpu_has_ds) {
|
|
unsigned int l1, l2;
|
|
rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
|
|
if (!(l1 & (1<<11)))
|
|
set_cpu_cap(c, X86_FEATURE_BTS);
|
|
if (!(l1 & (1<<12)))
|
|
set_cpu_cap(c, X86_FEATURE_PEBS);
|
|
}
|
|
|
|
|
|
if (cpu_has_bts)
|
|
ds_init_intel(c);
|
|
|
|
n = c->extended_cpuid_level;
|
|
if (n >= 0x80000008) {
|
|
unsigned eax = cpuid_eax(0x80000008);
|
|
c->x86_virt_bits = (eax >> 8) & 0xff;
|
|
c->x86_phys_bits = eax & 0xff;
|
|
/* CPUID workaround for Intel 0F34 CPU */
|
|
if (c->x86_vendor == X86_VENDOR_INTEL &&
|
|
c->x86 == 0xF && c->x86_model == 0x3 &&
|
|
c->x86_mask == 0x4)
|
|
c->x86_phys_bits = 36;
|
|
}
|
|
|
|
if (c->x86 == 15)
|
|
c->x86_cache_alignment = c->x86_clflush_size * 2;
|
|
if (c->x86 == 6)
|
|
set_cpu_cap(c, X86_FEATURE_REP_GOOD);
|
|
set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
|
|
c->x86_max_cores = intel_num_cpu_cores(c);
|
|
|
|
srat_detect_node();
|
|
}
|
|
|
|
static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
|
|
{
|
|
if (c->x86 == 0x6 && c->x86_model >= 0xf)
|
|
set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
|
|
}
|
|
|
|
static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
|
|
{
|
|
/* Cache sizes */
|
|
unsigned n;
|
|
|
|
n = c->extended_cpuid_level;
|
|
if (n >= 0x80000008) {
|
|
unsigned eax = cpuid_eax(0x80000008);
|
|
c->x86_virt_bits = (eax >> 8) & 0xff;
|
|
c->x86_phys_bits = eax & 0xff;
|
|
}
|
|
|
|
if (c->x86 == 0x6 && c->x86_model >= 0xf) {
|
|
c->x86_cache_alignment = c->x86_clflush_size * 2;
|
|
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
|
|
set_cpu_cap(c, X86_FEATURE_REP_GOOD);
|
|
}
|
|
set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
|
|
}
|
|
|
|
static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
|
|
{
|
|
char *v = c->x86_vendor_id;
|
|
|
|
if (!strcmp(v, "AuthenticAMD"))
|
|
c->x86_vendor = X86_VENDOR_AMD;
|
|
else if (!strcmp(v, "GenuineIntel"))
|
|
c->x86_vendor = X86_VENDOR_INTEL;
|
|
else if (!strcmp(v, "CentaurHauls"))
|
|
c->x86_vendor = X86_VENDOR_CENTAUR;
|
|
else
|
|
c->x86_vendor = X86_VENDOR_UNKNOWN;
|
|
}
|
|
|
|
/* Do some early cpuid on the boot CPU to get some parameter that are
|
|
needed before check_bugs. Everything advanced is in identify_cpu
|
|
below. */
|
|
static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
|
|
{
|
|
u32 tfms, xlvl;
|
|
|
|
c->loops_per_jiffy = loops_per_jiffy;
|
|
c->x86_cache_size = -1;
|
|
c->x86_vendor = X86_VENDOR_UNKNOWN;
|
|
c->x86_model = c->x86_mask = 0; /* So far unknown... */
|
|
c->x86_vendor_id[0] = '\0'; /* Unset */
|
|
c->x86_model_id[0] = '\0'; /* Unset */
|
|
c->x86_clflush_size = 64;
|
|
c->x86_cache_alignment = c->x86_clflush_size;
|
|
c->x86_max_cores = 1;
|
|
c->x86_coreid_bits = 0;
|
|
c->extended_cpuid_level = 0;
|
|
memset(&c->x86_capability, 0, sizeof c->x86_capability);
|
|
|
|
/* Get vendor name */
|
|
cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
|
|
(unsigned int *)&c->x86_vendor_id[0],
|
|
(unsigned int *)&c->x86_vendor_id[8],
|
|
(unsigned int *)&c->x86_vendor_id[4]);
|
|
|
|
get_cpu_vendor(c);
|
|
|
|
/* Initialize the standard set of capabilities */
|
|
/* Note that the vendor-specific code below might override */
|
|
|
|
/* Intel-defined flags: level 0x00000001 */
|
|
if (c->cpuid_level >= 0x00000001) {
|
|
__u32 misc;
|
|
cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
|
|
&c->x86_capability[0]);
|
|
c->x86 = (tfms >> 8) & 0xf;
|
|
c->x86_model = (tfms >> 4) & 0xf;
|
|
c->x86_mask = tfms & 0xf;
|
|
if (c->x86 == 0xf)
|
|
c->x86 += (tfms >> 20) & 0xff;
|
|
if (c->x86 >= 0x6)
|
|
c->x86_model += ((tfms >> 16) & 0xF) << 4;
|
|
if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
|
|
c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
|
|
} else {
|
|
/* Have CPUID level 0 only - unheard of */
|
|
c->x86 = 4;
|
|
}
|
|
|
|
c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
|
|
#ifdef CONFIG_SMP
|
|
c->phys_proc_id = c->initial_apicid;
|
|
#endif
|
|
/* AMD-defined flags: level 0x80000001 */
|
|
xlvl = cpuid_eax(0x80000000);
|
|
c->extended_cpuid_level = xlvl;
|
|
if ((xlvl & 0xffff0000) == 0x80000000) {
|
|
if (xlvl >= 0x80000001) {
|
|
c->x86_capability[1] = cpuid_edx(0x80000001);
|
|
c->x86_capability[6] = cpuid_ecx(0x80000001);
|
|
}
|
|
if (xlvl >= 0x80000004)
|
|
get_model_name(c); /* Default name */
|
|
}
|
|
|
|
/* Transmeta-defined flags: level 0x80860001 */
|
|
xlvl = cpuid_eax(0x80860000);
|
|
if ((xlvl & 0xffff0000) == 0x80860000) {
|
|
/* Don't set x86_cpuid_level here for now to not confuse. */
|
|
if (xlvl >= 0x80860001)
|
|
c->x86_capability[2] = cpuid_edx(0x80860001);
|
|
}
|
|
|
|
c->extended_cpuid_level = cpuid_eax(0x80000000);
|
|
if (c->extended_cpuid_level >= 0x80000007)
|
|
c->x86_power = cpuid_edx(0x80000007);
|
|
|
|
|
|
clear_cpu_cap(c, X86_FEATURE_PAT);
|
|
|
|
switch (c->x86_vendor) {
|
|
case X86_VENDOR_AMD:
|
|
early_init_amd(c);
|
|
if (c->x86 >= 0xf && c->x86 <= 0x11)
|
|
set_cpu_cap(c, X86_FEATURE_PAT);
|
|
break;
|
|
case X86_VENDOR_INTEL:
|
|
early_init_intel(c);
|
|
if (c->x86 == 0xF || (c->x86 == 6 && c->x86_model >= 15))
|
|
set_cpu_cap(c, X86_FEATURE_PAT);
|
|
break;
|
|
case X86_VENDOR_CENTAUR:
|
|
early_init_centaur(c);
|
|
break;
|
|
}
|
|
|
|
}
|
|
|
|
/*
|
|
* This does the hard work of actually picking apart the CPU stuff...
|
|
*/
|
|
void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
|
|
{
|
|
int i;
|
|
|
|
early_identify_cpu(c);
|
|
|
|
init_scattered_cpuid_features(c);
|
|
|
|
c->apicid = phys_pkg_id(0);
|
|
|
|
/*
|
|
* Vendor-specific initialization. In this section we
|
|
* canonicalize the feature flags, meaning if there are
|
|
* features a certain CPU supports which CPUID doesn't
|
|
* tell us, CPUID claiming incorrect flags, or other bugs,
|
|
* we handle them here.
|
|
*
|
|
* At the end of this section, c->x86_capability better
|
|
* indicate the features this CPU genuinely supports!
|
|
*/
|
|
switch (c->x86_vendor) {
|
|
case X86_VENDOR_AMD:
|
|
init_amd(c);
|
|
break;
|
|
|
|
case X86_VENDOR_INTEL:
|
|
init_intel(c);
|
|
break;
|
|
|
|
case X86_VENDOR_CENTAUR:
|
|
init_centaur(c);
|
|
break;
|
|
|
|
case X86_VENDOR_UNKNOWN:
|
|
default:
|
|
display_cacheinfo(c);
|
|
break;
|
|
}
|
|
|
|
detect_ht(c);
|
|
|
|
/*
|
|
* On SMP, boot_cpu_data holds the common feature set between
|
|
* all CPUs; so make sure that we indicate which features are
|
|
* common between the CPUs. The first time this routine gets
|
|
* executed, c == &boot_cpu_data.
|
|
*/
|
|
if (c != &boot_cpu_data) {
|
|
/* AND the already accumulated flags with these */
|
|
for (i = 0; i < NCAPINTS; i++)
|
|
boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
|
|
}
|
|
|
|
/* Clear all flags overriden by options */
|
|
for (i = 0; i < NCAPINTS; i++)
|
|
c->x86_capability[i] &= ~cleared_cpu_caps[i];
|
|
|
|
#ifdef CONFIG_X86_MCE
|
|
mcheck_init(c);
|
|
#endif
|
|
select_idle_routine(c);
|
|
|
|
#ifdef CONFIG_NUMA
|
|
numa_add_cpu(smp_processor_id());
|
|
#endif
|
|
|
|
}
|
|
|
|
void __cpuinit identify_boot_cpu(void)
|
|
{
|
|
identify_cpu(&boot_cpu_data);
|
|
}
|
|
|
|
void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
|
|
{
|
|
BUG_ON(c == &boot_cpu_data);
|
|
identify_cpu(c);
|
|
mtrr_ap_init();
|
|
}
|
|
|
|
static __init int setup_noclflush(char *arg)
|
|
{
|
|
setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
|
|
return 1;
|
|
}
|
|
__setup("noclflush", setup_noclflush);
|
|
|
|
void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
|
|
{
|
|
if (c->x86_model_id[0])
|
|
printk(KERN_CONT "%s", c->x86_model_id);
|
|
|
|
if (c->x86_mask || c->cpuid_level >= 0)
|
|
printk(KERN_CONT " stepping %02x\n", c->x86_mask);
|
|
else
|
|
printk(KERN_CONT "\n");
|
|
}
|
|
|
|
static __init int setup_disablecpuid(char *arg)
|
|
{
|
|
int bit;
|
|
if (get_option(&arg, &bit) && bit < NCAPINTS*32)
|
|
setup_clear_cpu_cap(bit);
|
|
else
|
|
return 0;
|
|
return 1;
|
|
}
|
|
__setup("clearcpuid=", setup_disablecpuid);
|