463 lines
13 KiB
C
463 lines
13 KiB
C
/*
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* arch/arm/mach-ixp2000/common.c
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*
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* Common routines used by all IXP2400/2800 based platforms.
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*
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* Author: Deepak Saxena <dsaxena@plexity.net>
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*
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* Copyright 2004 (C) MontaVista Software, Inc.
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*
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* Based on work Copyright (C) 2002-2003 Intel Corporation
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/serial.h>
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#include <linux/tty.h>
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#include <linux/bitops.h>
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#include <linux/serial_core.h>
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#include <linux/mm.h>
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#include <asm/types.h>
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#include <asm/setup.h>
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#include <asm/memory.h>
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#include <asm/hardware.h>
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#include <asm/mach-types.h>
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#include <asm/irq.h>
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#include <asm/system.h>
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#include <asm/tlbflush.h>
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#include <asm/pgtable.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/mach/irq.h>
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#include <asm/arch/gpio.h>
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static DEFINE_SPINLOCK(ixp2000_slowport_lock);
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static unsigned long ixp2000_slowport_irq_flags;
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/*************************************************************************
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* Slowport access routines
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*************************************************************************/
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void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
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{
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spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
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old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
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old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
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old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
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old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
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old_cfg->ADC = *IXP2000_SLOWPORT_ADC;
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ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
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ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
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ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
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ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
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ixp2000_reg_write(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
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}
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void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
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{
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ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
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ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
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ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
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ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
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ixp2000_reg_write(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
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spin_unlock_irqrestore(&ixp2000_slowport_lock,
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ixp2000_slowport_irq_flags);
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}
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/*************************************************************************
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* Chip specific mappings shared by all IXP2000 systems
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*************************************************************************/
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static struct map_desc ixp2000_io_desc[] __initdata = {
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{
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.virtual = IXP2000_CAP_VIRT_BASE,
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.physical = IXP2000_CAP_PHYS_BASE,
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.length = IXP2000_CAP_SIZE,
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.type = MT_DEVICE
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}, {
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.virtual = IXP2000_INTCTL_VIRT_BASE,
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.physical = IXP2000_INTCTL_PHYS_BASE,
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.length = IXP2000_INTCTL_SIZE,
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.type = MT_DEVICE
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}, {
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.virtual = IXP2000_PCI_CREG_VIRT_BASE,
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.physical = IXP2000_PCI_CREG_PHYS_BASE,
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.length = IXP2000_PCI_CREG_SIZE,
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.type = MT_DEVICE
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}, {
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.virtual = IXP2000_PCI_CSR_VIRT_BASE,
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.physical = IXP2000_PCI_CSR_PHYS_BASE,
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.length = IXP2000_PCI_CSR_SIZE,
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.type = MT_DEVICE
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}, {
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.virtual = IXP2000_MSF_VIRT_BASE,
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.physical = IXP2000_MSF_PHYS_BASE,
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.length = IXP2000_MSF_SIZE,
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.type = MT_DEVICE
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}, {
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.virtual = IXP2000_PCI_IO_VIRT_BASE,
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.physical = IXP2000_PCI_IO_PHYS_BASE,
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.length = IXP2000_PCI_IO_SIZE,
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.type = MT_DEVICE
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}, {
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.virtual = IXP2000_PCI_CFG0_VIRT_BASE,
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.physical = IXP2000_PCI_CFG0_PHYS_BASE,
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.length = IXP2000_PCI_CFG0_SIZE,
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.type = MT_DEVICE
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}, {
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.virtual = IXP2000_PCI_CFG1_VIRT_BASE,
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.physical = IXP2000_PCI_CFG1_PHYS_BASE,
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.length = IXP2000_PCI_CFG1_SIZE,
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.type = MT_DEVICE
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}
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};
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static struct uart_port ixp2000_serial_port = {
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.membase = (char *)(IXP2000_UART_VIRT_BASE + 3),
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.mapbase = IXP2000_UART_PHYS_BASE + 3,
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.irq = IRQ_IXP2000_UART,
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.flags = UPF_SKIP_TEST,
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.iotype = UPIO_MEM,
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.regshift = 2,
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.uartclk = 50000000,
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.line = 0,
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.type = PORT_XSCALE,
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.fifosize = 16
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};
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void __init ixp2000_map_io(void)
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{
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extern unsigned int processor_id;
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/*
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* On IXP2400 CPUs we need to use MT_IXP2000_DEVICE for
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* tweaking the PMDs so XCB=101. On IXP2800s we use the normal
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* PMD flags.
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*/
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if ((processor_id & 0xfffffff0) == 0x69054190) {
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int i;
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printk(KERN_INFO "Enabling IXP2400 erratum #66 workaround\n");
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for(i=0;i<ARRAY_SIZE(ixp2000_io_desc);i++)
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ixp2000_io_desc[i].type = MT_IXP2000_DEVICE;
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}
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iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
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early_serial_setup(&ixp2000_serial_port);
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/* Set slowport to 8-bit mode. */
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ixp2000_reg_write(IXP2000_SLOWPORT_FRM, 1);
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}
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/*************************************************************************
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* Timer-tick functions for IXP2000
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*************************************************************************/
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static unsigned ticks_per_jiffy;
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static unsigned ticks_per_usec;
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static unsigned next_jiffy_time;
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static volatile unsigned long *missing_jiffy_timer_csr;
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unsigned long ixp2000_gettimeoffset (void)
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{
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unsigned long offset;
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offset = next_jiffy_time - *missing_jiffy_timer_csr;
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return offset / ticks_per_usec;
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}
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static int ixp2000_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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write_seqlock(&xtime_lock);
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/* clear timer 1 */
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ixp2000_reg_write(IXP2000_T1_CLR, 1);
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while ((next_jiffy_time - *missing_jiffy_timer_csr) > ticks_per_jiffy) {
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timer_tick(regs);
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next_jiffy_time -= ticks_per_jiffy;
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}
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write_sequnlock(&xtime_lock);
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return IRQ_HANDLED;
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}
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static struct irqaction ixp2000_timer_irq = {
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.name = "IXP2000 Timer Tick",
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.flags = SA_INTERRUPT | SA_TIMER,
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.handler = ixp2000_timer_interrupt,
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};
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void __init ixp2000_init_time(unsigned long tick_rate)
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{
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ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
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ticks_per_usec = tick_rate / 1000000;
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/*
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* We use timer 1 as our timer interrupt.
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*/
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ixp2000_reg_write(IXP2000_T1_CLR, 0);
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ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
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ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
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/*
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* We use a second timer as a monotonic counter for tracking
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* missed jiffies. The IXP2000 has four timers, but if we're
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* on an A-step IXP2800, timer 2 and 3 don't work, so on those
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* chips we use timer 4. Timer 4 is the only timer that can
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* be used for the watchdog, so we use timer 2 if we're on a
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* non-buggy chip.
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*/
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if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
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printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");
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ixp2000_reg_write(IXP2000_T4_CLR, 0);
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ixp2000_reg_write(IXP2000_T4_CLD, -1);
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ixp2000_reg_write(IXP2000_T4_CTL, (1 << 7));
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missing_jiffy_timer_csr = IXP2000_T4_CSR;
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} else {
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ixp2000_reg_write(IXP2000_T2_CLR, 0);
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ixp2000_reg_write(IXP2000_T2_CLD, -1);
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ixp2000_reg_write(IXP2000_T2_CTL, (1 << 7));
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missing_jiffy_timer_csr = IXP2000_T2_CSR;
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}
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next_jiffy_time = 0xffffffff;
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/* register for interrupt */
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setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
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}
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/*************************************************************************
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* GPIO helpers
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*************************************************************************/
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static unsigned long GPIO_IRQ_falling_edge;
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static unsigned long GPIO_IRQ_rising_edge;
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static unsigned long GPIO_IRQ_level_low;
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static unsigned long GPIO_IRQ_level_high;
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static void update_gpio_int_csrs(void)
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{
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ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
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ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
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ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
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ixp2000_reg_write(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
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}
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void gpio_line_config(int line, int direction)
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{
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unsigned long flags;
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local_irq_save(flags);
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if (direction == GPIO_OUT) {
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irq_desc[line + IRQ_IXP2000_GPIO0].valid = 0;
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/* if it's an output, it ain't an interrupt anymore */
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GPIO_IRQ_falling_edge &= ~(1 << line);
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GPIO_IRQ_rising_edge &= ~(1 << line);
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GPIO_IRQ_level_low &= ~(1 << line);
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GPIO_IRQ_level_high &= ~(1 << line);
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update_gpio_int_csrs();
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ixp2000_reg_write(IXP2000_GPIO_PDSR, 1 << line);
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} else if (direction == GPIO_IN) {
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ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);
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}
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local_irq_restore(flags);
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}
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/*************************************************************************
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* IRQ handling IXP2000
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*************************************************************************/
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static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
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{
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int i;
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unsigned long status = *IXP2000_GPIO_INST;
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for (i = 0; i <= 7; i++) {
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if (status & (1<<i)) {
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desc = irq_desc + i + IRQ_IXP2000_GPIO0;
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desc->handle(i + IRQ_IXP2000_GPIO0, desc, regs);
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}
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}
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}
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static int ixp2000_GPIO_irq_type(unsigned int irq, unsigned int type)
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{
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int line = irq - IRQ_IXP2000_GPIO0;
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/*
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* First, configure this GPIO line as an input.
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*/
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ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);
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/*
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* Then, set the proper trigger type.
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*/
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if (type & IRQT_FALLING)
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GPIO_IRQ_falling_edge |= 1 << line;
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else
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GPIO_IRQ_falling_edge &= ~(1 << line);
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if (type & IRQT_RISING)
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GPIO_IRQ_rising_edge |= 1 << line;
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else
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GPIO_IRQ_rising_edge &= ~(1 << line);
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if (type & IRQT_LOW)
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GPIO_IRQ_level_low |= 1 << line;
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else
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GPIO_IRQ_level_low &= ~(1 << line);
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if (type & IRQT_HIGH)
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GPIO_IRQ_level_high |= 1 << line;
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else
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GPIO_IRQ_level_high &= ~(1 << line);
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update_gpio_int_csrs();
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/*
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* Finally, mark the corresponding IRQ as valid.
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*/
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irq_desc[irq].valid = 1;
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return 0;
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}
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static void ixp2000_GPIO_irq_mask_ack(unsigned int irq)
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{
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ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
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ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
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ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
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ixp2000_reg_write(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
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}
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static void ixp2000_GPIO_irq_mask(unsigned int irq)
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{
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ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
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}
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static void ixp2000_GPIO_irq_unmask(unsigned int irq)
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{
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ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
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}
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static struct irqchip ixp2000_GPIO_irq_chip = {
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.type = ixp2000_GPIO_irq_type,
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.ack = ixp2000_GPIO_irq_mask_ack,
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.mask = ixp2000_GPIO_irq_mask,
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.unmask = ixp2000_GPIO_irq_unmask
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};
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static void ixp2000_pci_irq_mask(unsigned int irq)
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{
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unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
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if (irq == IRQ_IXP2000_PCIA)
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ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
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else if (irq == IRQ_IXP2000_PCIB)
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ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
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}
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static void ixp2000_pci_irq_unmask(unsigned int irq)
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{
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unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
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if (irq == IRQ_IXP2000_PCIA)
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ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
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else if (irq == IRQ_IXP2000_PCIB)
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ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
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}
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static struct irqchip ixp2000_pci_irq_chip = {
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.ack = ixp2000_pci_irq_mask,
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.mask = ixp2000_pci_irq_mask,
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.unmask = ixp2000_pci_irq_unmask
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};
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static void ixp2000_irq_mask(unsigned int irq)
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{
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ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
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}
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static void ixp2000_irq_unmask(unsigned int irq)
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{
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ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq));
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}
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static struct irqchip ixp2000_irq_chip = {
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.ack = ixp2000_irq_mask,
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.mask = ixp2000_irq_mask,
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.unmask = ixp2000_irq_unmask
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};
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void __init ixp2000_init_irq(void)
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{
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int irq;
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/*
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* Mask all sources
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*/
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ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
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ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);
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/* clear all GPIO edge/level detects */
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ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
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ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
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ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
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ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
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ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
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/* clear PCI interrupt sources */
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ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
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/*
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* Certain bits in the IRQ status register of the
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* IXP2000 are reserved. Instead of trying to map
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* things non 1:1 from bit position to IRQ number,
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* we mark the reserved IRQs as invalid. This makes
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* our mask/unmask code much simpler.
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*/
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for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
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if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
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set_irq_chip(irq, &ixp2000_irq_chip);
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set_irq_handler(irq, do_level_IRQ);
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set_irq_flags(irq, IRQF_VALID);
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} else set_irq_flags(irq, 0);
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}
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/*
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* GPIO IRQs are invalid until someone sets the interrupt mode
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* by calling set_irq_type().
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*/
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for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
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set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
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set_irq_handler(irq, do_level_IRQ);
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set_irq_flags(irq, 0);
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}
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set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
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/*
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* Enable PCI irqs. The actual PCI[AB] decoding is done in
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* entry-macro.S, so we don't need a chained handler for the
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* PCI interrupt source.
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*/
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ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
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for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
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set_irq_chip(irq, &ixp2000_pci_irq_chip);
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set_irq_handler(irq, do_level_IRQ);
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set_irq_flags(irq, IRQF_VALID);
|
|
}
|
|
}
|
|
|