393 lines
9.2 KiB
C
393 lines
9.2 KiB
C
/*
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* linux/arch/arm/kernel/dec21285.c: PCI functions for DC21285
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*
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* Copyright (C) 1998-2001 Russell King
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* Copyright (C) 1998-2000 Phil Blundell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <video/vga.h>
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#include <asm/irq.h>
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#include <asm/system.h>
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#include <asm/mach/pci.h>
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#include <asm/hardware/dec21285.h>
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#define MAX_SLOTS 21
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#define PCICMD_ABORT ((PCI_STATUS_REC_MASTER_ABORT| \
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PCI_STATUS_REC_TARGET_ABORT)<<16)
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#define PCICMD_ERROR_BITS ((PCI_STATUS_DETECTED_PARITY | \
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PCI_STATUS_REC_MASTER_ABORT | \
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PCI_STATUS_REC_TARGET_ABORT | \
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PCI_STATUS_PARITY) << 16)
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extern int setup_arm_irq(int, struct irqaction *);
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extern void pcibios_report_status(u_int status_mask, int warn);
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static unsigned long
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dc21285_base_address(struct pci_bus *bus, unsigned int devfn)
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{
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unsigned long addr = 0;
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if (bus->number == 0) {
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if (PCI_SLOT(devfn) == 0)
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/*
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* For devfn 0, point at the 21285
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*/
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addr = ARMCSR_BASE;
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else {
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devfn -= 1 << 3;
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if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
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addr = PCICFG0_BASE | 0xc00000 | (devfn << 8);
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}
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} else
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addr = PCICFG1_BASE | (bus->number << 16) | (devfn << 8);
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return addr;
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}
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static int
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dc21285_read_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *value)
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{
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unsigned long addr = dc21285_base_address(bus, devfn);
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u32 v = 0xffffffff;
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if (addr)
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switch (size) {
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case 1:
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asm("ldrb %0, [%1, %2]"
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: "=r" (v) : "r" (addr), "r" (where) : "cc");
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break;
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case 2:
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asm("ldrh %0, [%1, %2]"
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: "=r" (v) : "r" (addr), "r" (where) : "cc");
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break;
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case 4:
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asm("ldr %0, [%1, %2]"
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: "=r" (v) : "r" (addr), "r" (where) : "cc");
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break;
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}
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*value = v;
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v = *CSR_PCICMD;
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if (v & PCICMD_ABORT) {
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*CSR_PCICMD = v & (0xffff|PCICMD_ABORT);
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return -1;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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dc21285_write_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 value)
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{
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unsigned long addr = dc21285_base_address(bus, devfn);
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u32 v;
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if (addr)
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switch (size) {
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case 1:
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asm("strb %0, [%1, %2]"
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: : "r" (value), "r" (addr), "r" (where)
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: "cc");
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break;
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case 2:
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asm("strh %0, [%1, %2]"
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: : "r" (value), "r" (addr), "r" (where)
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: "cc");
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break;
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case 4:
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asm("str %0, [%1, %2]"
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: : "r" (value), "r" (addr), "r" (where)
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: "cc");
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break;
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}
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v = *CSR_PCICMD;
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if (v & PCICMD_ABORT) {
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*CSR_PCICMD = v & (0xffff|PCICMD_ABORT);
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return -1;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops dc21285_ops = {
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.read = dc21285_read_config,
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.write = dc21285_write_config,
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};
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static struct timer_list serr_timer;
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static struct timer_list perr_timer;
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static void dc21285_enable_error(unsigned long __data)
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{
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switch (__data) {
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case IRQ_PCI_SERR:
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del_timer(&serr_timer);
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break;
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case IRQ_PCI_PERR:
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del_timer(&perr_timer);
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break;
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}
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enable_irq(__data);
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}
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/*
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* Warn on PCI errors.
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*/
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static irqreturn_t dc21285_abort_irq(int irq, void *dev_id)
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{
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unsigned int cmd;
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unsigned int status;
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cmd = *CSR_PCICMD;
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status = cmd >> 16;
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cmd = cmd & 0xffff;
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if (status & PCI_STATUS_REC_MASTER_ABORT) {
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printk(KERN_DEBUG "PCI: master abort, pc=0x%08lx\n",
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instruction_pointer(get_irq_regs()));
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cmd |= PCI_STATUS_REC_MASTER_ABORT << 16;
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}
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if (status & PCI_STATUS_REC_TARGET_ABORT) {
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printk(KERN_DEBUG "PCI: target abort: ");
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pcibios_report_status(PCI_STATUS_REC_MASTER_ABORT |
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PCI_STATUS_SIG_TARGET_ABORT |
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PCI_STATUS_REC_TARGET_ABORT, 1);
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printk("\n");
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cmd |= PCI_STATUS_REC_TARGET_ABORT << 16;
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}
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*CSR_PCICMD = cmd;
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return IRQ_HANDLED;
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}
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static irqreturn_t dc21285_serr_irq(int irq, void *dev_id)
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{
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struct timer_list *timer = dev_id;
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unsigned int cntl;
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printk(KERN_DEBUG "PCI: system error received: ");
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pcibios_report_status(PCI_STATUS_SIG_SYSTEM_ERROR, 1);
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printk("\n");
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cntl = *CSR_SA110_CNTL & 0xffffdf07;
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*CSR_SA110_CNTL = cntl | SA110_CNTL_RXSERR;
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/*
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* back off this interrupt
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*/
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disable_irq(irq);
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timer->expires = jiffies + HZ;
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add_timer(timer);
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return IRQ_HANDLED;
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}
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static irqreturn_t dc21285_discard_irq(int irq, void *dev_id)
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{
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printk(KERN_DEBUG "PCI: discard timer expired\n");
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*CSR_SA110_CNTL &= 0xffffde07;
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return IRQ_HANDLED;
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}
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static irqreturn_t dc21285_dparity_irq(int irq, void *dev_id)
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{
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unsigned int cmd;
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printk(KERN_DEBUG "PCI: data parity error detected: ");
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pcibios_report_status(PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY, 1);
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printk("\n");
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cmd = *CSR_PCICMD & 0xffff;
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*CSR_PCICMD = cmd | 1 << 24;
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return IRQ_HANDLED;
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}
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static irqreturn_t dc21285_parity_irq(int irq, void *dev_id)
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{
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struct timer_list *timer = dev_id;
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unsigned int cmd;
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printk(KERN_DEBUG "PCI: parity error detected: ");
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pcibios_report_status(PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY, 1);
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printk("\n");
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cmd = *CSR_PCICMD & 0xffff;
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*CSR_PCICMD = cmd | 1 << 31;
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/*
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* back off this interrupt
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*/
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disable_irq(irq);
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timer->expires = jiffies + HZ;
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add_timer(timer);
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return IRQ_HANDLED;
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}
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int __init dc21285_setup(int nr, struct pci_sys_data *sys)
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{
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struct resource *res;
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if (nr || !footbridge_cfn_mode())
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return 0;
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res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
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if (!res) {
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printk("out of memory for root bus resources");
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return 0;
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}
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res[0].flags = IORESOURCE_MEM;
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res[0].name = "Footbridge non-prefetch";
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res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
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res[1].name = "Footbridge prefetch";
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allocate_resource(&iomem_resource, &res[1], 0x20000000,
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0xa0000000, 0xffffffff, 0x20000000, NULL, NULL);
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allocate_resource(&iomem_resource, &res[0], 0x40000000,
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0x80000000, 0xffffffff, 0x40000000, NULL, NULL);
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sys->resource[0] = &ioport_resource;
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sys->resource[1] = &res[0];
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sys->resource[2] = &res[1];
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sys->mem_offset = DC21285_PCI_MEM;
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return 1;
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}
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struct pci_bus * __init dc21285_scan_bus(int nr, struct pci_sys_data *sys)
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{
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return pci_scan_bus(0, &dc21285_ops, sys);
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}
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#define dc21285_request_irq(_a, _b, _c, _d, _e) \
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WARN_ON(request_irq(_a, _b, _c, _d, _e) < 0)
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void __init dc21285_preinit(void)
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{
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unsigned int mem_size, mem_mask;
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int cfn_mode;
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pcibios_min_mem = 0x81000000;
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vga_base = PCIMEM_BASE;
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mem_size = (unsigned int)high_memory - PAGE_OFFSET;
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for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1)
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if (mem_mask >= mem_size)
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break;
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/*
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* These registers need to be set up whether we're the
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* central function or not.
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*/
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*CSR_SDRAMBASEMASK = (mem_mask - 1) & 0x0ffc0000;
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*CSR_SDRAMBASEOFFSET = 0;
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*CSR_ROMBASEMASK = 0x80000000;
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*CSR_CSRBASEMASK = 0;
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*CSR_CSRBASEOFFSET = 0;
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*CSR_PCIADDR_EXTN = 0;
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cfn_mode = __footbridge_cfn_mode();
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printk(KERN_INFO "PCI: DC21285 footbridge, revision %02lX, in "
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"%s mode\n", *CSR_CLASSREV & 0xff, cfn_mode ?
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"central function" : "addin");
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if (footbridge_cfn_mode()) {
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/*
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* Clear any existing errors - we aren't
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* interested in historical data...
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*/
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*CSR_SA110_CNTL = (*CSR_SA110_CNTL & 0xffffde07) |
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SA110_CNTL_RXSERR;
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*CSR_PCICMD = (*CSR_PCICMD & 0xffff) | PCICMD_ERROR_BITS;
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}
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init_timer(&serr_timer);
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init_timer(&perr_timer);
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serr_timer.data = IRQ_PCI_SERR;
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serr_timer.function = dc21285_enable_error;
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perr_timer.data = IRQ_PCI_PERR;
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perr_timer.function = dc21285_enable_error;
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/*
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* We don't care if these fail.
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*/
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dc21285_request_irq(IRQ_PCI_SERR, dc21285_serr_irq, IRQF_DISABLED,
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"PCI system error", &serr_timer);
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dc21285_request_irq(IRQ_PCI_PERR, dc21285_parity_irq, IRQF_DISABLED,
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"PCI parity error", &perr_timer);
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dc21285_request_irq(IRQ_PCI_ABORT, dc21285_abort_irq, IRQF_DISABLED,
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"PCI abort", NULL);
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dc21285_request_irq(IRQ_DISCARD_TIMER, dc21285_discard_irq, IRQF_DISABLED,
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"Discard timer", NULL);
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dc21285_request_irq(IRQ_PCI_DPERR, dc21285_dparity_irq, IRQF_DISABLED,
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"PCI data parity", NULL);
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if (cfn_mode) {
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static struct resource csrio;
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csrio.flags = IORESOURCE_IO;
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csrio.name = "Footbridge";
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allocate_resource(&ioport_resource, &csrio, 128,
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0xff00, 0xffff, 128, NULL, NULL);
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/*
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* Map our SDRAM at a known address in PCI space, just in case
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* the firmware had other ideas. Using a nonzero base is
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* necessary, since some VGA cards forcefully use PCI addresses
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* in the range 0x000a0000 to 0x000c0000. (eg, S3 cards).
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*/
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*CSR_PCICSRBASE = 0xf4000000;
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*CSR_PCICSRIOBASE = csrio.start;
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*CSR_PCISDRAMBASE = __virt_to_bus(PAGE_OFFSET);
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*CSR_PCIROMBASE = 0;
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*CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
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PCI_COMMAND_INVALIDATE | PCICMD_ERROR_BITS;
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} else if (footbridge_cfn_mode() != 0) {
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/*
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* If we are not compiled to accept "add-in" mode, then
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* we are using a constant virt_to_bus translation which
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* can not hope to cater for the way the host BIOS has
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* set up the machine.
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*/
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panic("PCI: this kernel is compiled for central "
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"function mode only");
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}
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}
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void __init dc21285_postinit(void)
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{
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register_isa_ports(DC21285_PCI_MEM, DC21285_PCI_IO, 0);
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}
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