245 lines
5.7 KiB
C
245 lines
5.7 KiB
C
/*
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* linux/arch/arm/mach-h720x/common.c
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*
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* Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
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* 2003 Robert Schwebel <r.schwebel@pengutronix.de>
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* 2004 Sascha Hauer <s.hauer@pengutronix.de>
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*
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* common stuff for Hynix h720x processors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/sched.h>
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#include <linux/mman.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/dma.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/map.h>
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#include <mach/irqs.h>
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#include <asm/mach/dma.h>
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#if 0
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#define IRQDBG(args...) printk(args)
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#else
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#define IRQDBG(args...) do {} while(0)
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#endif
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void __init arch_dma_init(dma_t *dma)
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{
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}
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/*
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* Return usecs since last timer reload
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* (timercount * (usecs perjiffie)) / (ticks per jiffie)
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*/
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unsigned long h720x_gettimeoffset(void)
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{
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return (CPU_REG (TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH;
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}
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/*
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* mask Global irq's
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*/
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static void mask_global_irq(struct irq_data *d)
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{
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CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << d->irq);
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}
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/*
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* unmask Global irq's
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*/
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static void unmask_global_irq(struct irq_data *d)
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{
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CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << d->irq);
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}
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/*
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* ack GPIO irq's
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* Ack only for edge triggered int's valid
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*/
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static void inline ack_gpio_irq(struct irq_data *d)
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{
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u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq));
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u32 bit = IRQ_TO_BIT(d->irq);
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if ( (CPU_REG (reg_base, GPIO_EDGE) & bit))
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CPU_REG (reg_base, GPIO_CLR) = bit;
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}
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/*
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* mask GPIO irq's
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*/
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static void inline mask_gpio_irq(struct irq_data *d)
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{
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u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq));
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u32 bit = IRQ_TO_BIT(d->irq);
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CPU_REG (reg_base, GPIO_MASK) &= ~bit;
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}
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/*
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* unmask GPIO irq's
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*/
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static void inline unmask_gpio_irq(struct irq_data *d)
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{
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u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq));
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u32 bit = IRQ_TO_BIT(d->irq);
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CPU_REG (reg_base, GPIO_MASK) |= bit;
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}
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static void
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h720x_gpio_handler(unsigned int mask, unsigned int irq,
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struct irq_desc *desc)
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{
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IRQDBG("%s irq: %d\n", __func__, irq);
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while (mask) {
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if (mask & 1) {
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IRQDBG("handling irq %d\n", irq);
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generic_handle_irq(irq);
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}
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irq++;
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mask >>= 1;
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}
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}
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static void
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h720x_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
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{
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unsigned int mask, irq;
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mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT);
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irq = IRQ_CHAINED_GPIOA(0);
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IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
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h720x_gpio_handler(mask, irq, desc);
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}
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static void
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h720x_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
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{
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unsigned int mask, irq;
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mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT);
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irq = IRQ_CHAINED_GPIOB(0);
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IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
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h720x_gpio_handler(mask, irq, desc);
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}
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static void
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h720x_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
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{
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unsigned int mask, irq;
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mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT);
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irq = IRQ_CHAINED_GPIOC(0);
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IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
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h720x_gpio_handler(mask, irq, desc);
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}
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static void
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h720x_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
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{
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unsigned int mask, irq;
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mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT);
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irq = IRQ_CHAINED_GPIOD(0);
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IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
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h720x_gpio_handler(mask, irq, desc);
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}
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#ifdef CONFIG_CPU_H7202
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static void
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h720x_gpioe_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
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{
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unsigned int mask, irq;
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mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT);
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irq = IRQ_CHAINED_GPIOE(0);
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IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
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h720x_gpio_handler(mask, irq, desc);
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}
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#endif
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static struct irq_chip h720x_global_chip = {
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.irq_ack = mask_global_irq,
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.irq_mask = mask_global_irq,
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.irq_unmask = unmask_global_irq,
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};
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static struct irq_chip h720x_gpio_chip = {
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.irq_ack = ack_gpio_irq,
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.irq_mask = mask_gpio_irq,
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.irq_unmask = unmask_gpio_irq,
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};
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/*
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* Initialize IRQ's, mask all, enable multiplexed irq's
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*/
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void __init h720x_init_irq (void)
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{
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int irq;
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/* Mask global irq's */
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CPU_REG (IRQC_VIRT, IRQC_IER) = 0x0;
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/* Mask all multiplexed irq's */
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CPU_REG (GPIO_A_VIRT, GPIO_MASK) = 0x0;
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CPU_REG (GPIO_B_VIRT, GPIO_MASK) = 0x0;
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CPU_REG (GPIO_C_VIRT, GPIO_MASK) = 0x0;
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CPU_REG (GPIO_D_VIRT, GPIO_MASK) = 0x0;
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/* Initialize global IRQ's, fast path */
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for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
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irq_set_chip_and_handler(irq, &h720x_global_chip,
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handle_level_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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/* Initialize multiplexed IRQ's, slow path */
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for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
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irq_set_chip_and_handler(irq, &h720x_gpio_chip,
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handle_edge_irq);
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set_irq_flags(irq, IRQF_VALID );
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}
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irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
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irq_set_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
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irq_set_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
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irq_set_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
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#ifdef CONFIG_CPU_H7202
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for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
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irq_set_chip_and_handler(irq, &h720x_gpio_chip,
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handle_edge_irq);
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set_irq_flags(irq, IRQF_VALID );
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}
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irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
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#endif
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/* Enable multiplexed irq's */
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CPU_REG (IRQC_VIRT, IRQC_IER) = IRQ_ENA_MUX;
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}
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static struct map_desc h720x_io_desc[] __initdata = {
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{
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.virtual = IO_VIRT,
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.pfn = __phys_to_pfn(IO_PHYS),
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.length = IO_SIZE,
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.type = MT_DEVICE
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},
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};
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/* Initialize io tables */
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void __init h720x_map_io(void)
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{
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iotable_init(h720x_io_desc,ARRAY_SIZE(h720x_io_desc));
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}
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