250 lines
6.1 KiB
C
250 lines
6.1 KiB
C
/*
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* arch/arm/plat-spear/include/plat/clock.h
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*
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* Clock framework definitions for SPEAr platform
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*
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* Copyright (C) 2009 ST Microelectronics
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* Viresh Kumar<viresh.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __PLAT_CLOCK_H
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#define __PLAT_CLOCK_H
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#include <linux/list.h>
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#include <linux/clkdev.h>
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#include <linux/types.h>
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/* clk structure flags */
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#define ALWAYS_ENABLED (1 << 0) /* clock always enabled */
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#define RESET_TO_ENABLE (1 << 1) /* reset register bit to enable clk */
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#define ENABLED_ON_INIT (1 << 2) /* clocks enabled at init */
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/**
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* struct clkops - clock operations
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* @enable: pointer to clock enable function
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* @disable: pointer to clock disable function
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*/
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struct clkops {
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int (*enable) (struct clk *);
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void (*disable) (struct clk *);
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};
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/**
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* struct pclk_info - parents info
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* @pclk: pointer to parent clk
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* @pclk_val: value to be written for selecting this parent
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*/
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struct pclk_info {
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struct clk *pclk;
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u8 pclk_val;
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};
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/**
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* struct pclk_sel - parents selection configuration
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* @pclk_info: pointer to array of parent clock info
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* @pclk_count: number of parents
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* @pclk_sel_reg: register for selecting a parent
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* @pclk_sel_mask: mask for selecting parent (can be used to clear bits also)
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*/
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struct pclk_sel {
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struct pclk_info *pclk_info;
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u8 pclk_count;
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void __iomem *pclk_sel_reg;
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unsigned int pclk_sel_mask;
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};
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/**
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* struct rate_config - clk rate configurations
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* @tbls: array of device specific clk rate tables, in ascending order of rates
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* @count: size of tbls array
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* @default_index: default setting when originally disabled
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*/
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struct rate_config {
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void *tbls;
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u8 count;
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u8 default_index;
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};
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/**
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* struct clk - clock structure
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* @usage_count: num of users who enabled this clock
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* @flags: flags for clock properties
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* @rate: programmed clock rate in Hz
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* @en_reg: clk enable/disable reg
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* @en_reg_bit: clk enable/disable bit
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* @ops: clk enable/disable ops - generic_clkops selected if NULL
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* @recalc: pointer to clock rate recalculate function
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* @set_rate: pointer to clock set rate function
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* @calc_rate: pointer to clock get rate function for index
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* @rate_config: rate configuration information, used by set_rate
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* @div_factor: division factor to parent clock.
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* @pclk: current parent clk
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* @pclk_sel: pointer to parent selection structure
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* @pclk_sel_shift: register shift for selecting parent of this clock
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* @children: list for childrens or this clock
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* @sibling: node for list of clocks having same parents
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* @private_data: clock specific private data
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* @node: list to maintain clocks linearly
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* @cl: clocklook up associated with this clock
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* @dent: object for debugfs
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*/
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struct clk {
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unsigned int usage_count;
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unsigned int flags;
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unsigned long rate;
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void __iomem *en_reg;
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u8 en_reg_bit;
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const struct clkops *ops;
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int (*recalc) (struct clk *);
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int (*set_rate) (struct clk *, unsigned long rate);
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unsigned long (*calc_rate)(struct clk *, int index);
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struct rate_config rate_config;
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unsigned int div_factor;
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struct clk *pclk;
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struct pclk_sel *pclk_sel;
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unsigned int pclk_sel_shift;
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struct list_head children;
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struct list_head sibling;
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void *private_data;
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#ifdef CONFIG_DEBUG_FS
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struct list_head node;
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struct clk_lookup *cl;
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struct dentry *dent;
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#endif
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};
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/* pll configuration structure */
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struct pll_clk_masks {
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u32 mode_mask;
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u32 mode_shift;
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u32 norm_fdbk_m_mask;
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u32 norm_fdbk_m_shift;
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u32 dith_fdbk_m_mask;
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u32 dith_fdbk_m_shift;
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u32 div_p_mask;
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u32 div_p_shift;
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u32 div_n_mask;
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u32 div_n_shift;
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};
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struct pll_clk_config {
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void __iomem *mode_reg;
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void __iomem *cfg_reg;
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struct pll_clk_masks *masks;
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};
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/* pll clk rate config structure */
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struct pll_rate_tbl {
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u8 mode;
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u16 m;
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u8 n;
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u8 p;
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};
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/* ahb and apb bus configuration structure */
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struct bus_clk_masks {
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u32 mask;
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u32 shift;
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};
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struct bus_clk_config {
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void __iomem *reg;
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struct bus_clk_masks *masks;
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};
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/* ahb and apb clk bus rate config structure */
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struct bus_rate_tbl {
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u8 div;
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};
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/* Aux clk configuration structure: applicable to UART and FIRDA */
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struct aux_clk_masks {
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u32 eq_sel_mask;
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u32 eq_sel_shift;
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u32 eq1_mask;
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u32 eq2_mask;
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u32 xscale_sel_mask;
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u32 xscale_sel_shift;
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u32 yscale_sel_mask;
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u32 yscale_sel_shift;
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};
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struct aux_clk_config {
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void __iomem *synth_reg;
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struct aux_clk_masks *masks;
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};
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/* aux clk rate config structure */
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struct aux_rate_tbl {
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u16 xscale;
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u16 yscale;
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u8 eq;
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};
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/* GPT clk configuration structure */
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struct gpt_clk_masks {
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u32 mscale_sel_mask;
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u32 mscale_sel_shift;
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u32 nscale_sel_mask;
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u32 nscale_sel_shift;
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};
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struct gpt_clk_config {
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void __iomem *synth_reg;
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struct gpt_clk_masks *masks;
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};
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/* gpt clk rate config structure */
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struct gpt_rate_tbl {
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u16 mscale;
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u16 nscale;
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};
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/* clcd clk configuration structure */
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struct clcd_synth_masks {
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u32 div_factor_mask;
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u32 div_factor_shift;
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};
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struct clcd_clk_config {
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void __iomem *synth_reg;
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struct clcd_synth_masks *masks;
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};
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/* clcd clk rate config structure */
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struct clcd_rate_tbl {
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u16 div;
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};
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/* platform specific clock functions */
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void __init clk_init(void);
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void clk_register(struct clk_lookup *cl);
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void recalc_root_clocks(void);
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/* clock recalc & set rate functions */
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int follow_parent(struct clk *clk);
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unsigned long pll_calc_rate(struct clk *clk, int index);
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int pll_clk_recalc(struct clk *clk);
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int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate);
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unsigned long bus_calc_rate(struct clk *clk, int index);
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int bus_clk_recalc(struct clk *clk);
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int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate);
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unsigned long gpt_calc_rate(struct clk *clk, int index);
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int gpt_clk_recalc(struct clk *clk);
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int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate);
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unsigned long aux_calc_rate(struct clk *clk, int index);
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int aux_clk_recalc(struct clk *clk);
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int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate);
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unsigned long clcd_calc_rate(struct clk *clk, int index);
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int clcd_clk_recalc(struct clk *clk);
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int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate);
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#endif /* __PLAT_CLOCK_H */
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