165 lines
3.6 KiB
C
165 lines
3.6 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* SNI specific PCI support for RM200/RM300.
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*
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* Copyright (C) 1997 - 2000, 2003 Ralf Baechle <ralf@linux-mips.org>
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/types.h>
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#include <asm/sni.h>
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/*
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* It seems that on the RM200 only lower 3 bits of the 5 bit PCI device
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* address are decoded. We therefore manually have to reject attempts at
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* reading outside this range. Being on the paranoid side we only do this
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* test for bus 0 and hope forwarding and decoding work properly for any
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* subordinated busses.
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*
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* ASIC PCI only supports type 1 config cycles.
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*/
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static int set_config_address(unsigned int busno, unsigned int devfn, int reg)
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{
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if ((devfn > 255) || (reg > 255))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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if (busno == 0 && devfn >= PCI_DEVFN(8, 0))
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return PCIBIOS_DEVICE_NOT_FOUND;
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*(volatile u32 *)PCIMT_CONFIG_ADDRESS =
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((busno & 0xff) << 16) |
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((devfn & 0xff) << 8) |
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(reg & 0xfc);
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return PCIBIOS_SUCCESSFUL;
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}
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static int pcimt_read(struct pci_bus *bus, unsigned int devfn, int reg,
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int size, u32 * val)
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{
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int res;
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if ((res = set_config_address(bus->number, devfn, reg)))
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return res;
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switch (size) {
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case 1:
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*val = inb(PCIMT_CONFIG_DATA + (reg & 3));
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break;
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case 2:
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*val = inw(PCIMT_CONFIG_DATA + (reg & 2));
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break;
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case 4:
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*val = inl(PCIMT_CONFIG_DATA);
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break;
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}
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return 0;
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}
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static int pcimt_write(struct pci_bus *bus, unsigned int devfn, int reg,
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int size, u32 val)
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{
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int res;
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if ((res = set_config_address(bus->number, devfn, reg)))
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return res;
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switch (size) {
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case 1:
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outb(val, PCIMT_CONFIG_DATA + (reg & 3));
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break;
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case 2:
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outw(val, PCIMT_CONFIG_DATA + (reg & 2));
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break;
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case 4:
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outl(val, PCIMT_CONFIG_DATA);
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break;
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}
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return 0;
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}
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struct pci_ops sni_pcimt_ops = {
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.read = pcimt_read,
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.write = pcimt_write,
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};
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static int pcit_set_config_address(unsigned int busno, unsigned int devfn, int reg)
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{
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if ((devfn > 255) || (reg > 255) || (busno > 255))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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outl((1 << 31) | ((busno & 0xff) << 16) | ((devfn & 0xff) << 8) | (reg & 0xfc), 0xcf8);
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return PCIBIOS_SUCCESSFUL;
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}
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static int pcit_read(struct pci_bus *bus, unsigned int devfn, int reg,
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int size, u32 * val)
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{
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int res;
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/*
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* on bus 0 we need to check, whether there is a device answering
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* for the devfn by doing a config write and checking the result. If
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* we don't do it, we will get a data bus error
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*/
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if (bus->number == 0) {
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pcit_set_config_address(0, 0, 0x68);
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outl(inl(0xcfc) | 0xc0000000, 0xcfc);
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if ((res = pcit_set_config_address(0, devfn, 0)))
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return res;
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outl(0xffffffff, 0xcfc);
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pcit_set_config_address(0, 0, 0x68);
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if (inl(0xcfc) & 0x100000)
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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if ((res = pcit_set_config_address(bus->number, devfn, reg)))
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return res;
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switch (size) {
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case 1:
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*val = inb(PCIMT_CONFIG_DATA + (reg & 3));
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break;
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case 2:
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*val = inw(PCIMT_CONFIG_DATA + (reg & 2));
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break;
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case 4:
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*val = inl(PCIMT_CONFIG_DATA);
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break;
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}
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return 0;
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}
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static int pcit_write(struct pci_bus *bus, unsigned int devfn, int reg,
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int size, u32 val)
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{
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int res;
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if ((res = pcit_set_config_address(bus->number, devfn, reg)))
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return res;
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switch (size) {
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case 1:
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outb(val, PCIMT_CONFIG_DATA + (reg & 3));
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break;
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case 2:
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outw(val, PCIMT_CONFIG_DATA + (reg & 2));
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break;
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case 4:
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outl(val, PCIMT_CONFIG_DATA);
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break;
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}
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return 0;
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}
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struct pci_ops sni_pcit_ops = {
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.read = pcit_read,
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.write = pcit_write,
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};
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