196 lines
5.3 KiB
C
196 lines
5.3 KiB
C
/*
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* Embedded Planet 405GP board
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* http://www.embeddedplanet.com
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*
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* Author: Matthew Locke <mlocke@mvista.com>
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*
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* 2001 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <asm/system.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include <asm/todc.h>
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#include <asm/ocp.h>
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#include <asm/ibm_ocp_pci.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(x...) printk(x)
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#else
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#define DBG(x...)
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#endif
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u8 *ep405_bcsr;
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u8 *ep405_nvram;
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static struct {
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u8 cpld_xirq_select;
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int pci_idsel;
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int irq;
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} ep405_devtable[] = {
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#ifdef CONFIG_EP405PC
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{0x07, 0x0E, 25}, /* EP405PC: USB */
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#endif
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};
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int __init
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ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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int i;
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/* AFAICT this is only called a few times during PCI setup, so
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performance is not critical */
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for (i = 0; i < ARRAY_SIZE(ep405_devtable); i++) {
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if (idsel == ep405_devtable[i].pci_idsel)
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return ep405_devtable[i].irq;
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}
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return -1;
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};
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void __init
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ep405_setup_arch(void)
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{
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ppc4xx_setup_arch();
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ibm_ocp_set_emac(0, 0);
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if (__res.bi_nvramsize == 512*1024) {
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/* FIXME: we should properly handle NVRTCs of different sizes */
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TODC_INIT(TODC_TYPE_DS1557, ep405_nvram, ep405_nvram, ep405_nvram, 8);
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}
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}
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void __init
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bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
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{
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unsigned int bar_response, bar;
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/*
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* Expected PCI mapping:
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*
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* PLB addr PCI memory addr
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* --------------------- ---------------------
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* 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
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* 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
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*
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* PLB addr PCI io addr
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* --------------------- ---------------------
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* e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
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*
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*/
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/* Disable region zero first */
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out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
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/* PLB starting addr, PCI: 0x80000000 */
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out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
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/* PCI start addr, 0x80000000 */
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out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
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/* 512MB range of PLB to PCI */
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out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
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/* Enable no pre-fetch, enable region */
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out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
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(PPC405_PCI_UPPER_MEM -
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PPC405_PCI_MEM_BASE)) | 0x01));
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/* Disable region one */
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out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
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out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
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out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
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out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
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out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
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out_le32((void *) &(pcip->ptm1ms), 0x00000000);
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/* Disable region two */
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out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
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out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
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out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
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out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
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out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
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out_le32((void *) &(pcip->ptm2ms), 0x00000000);
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/* Configure PTM (PCI->PLB) region 1 */
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out_le32((void *) &(pcip->ptm1la), 0x00000000); /* PLB base address */
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/* Disable PTM region 2 */
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out_le32((void *) &(pcip->ptm2ms), 0x00000000);
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/* Zero config bars */
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for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
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early_write_config_dword(hose, hose->first_busno,
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PCI_FUNC(hose->first_busno), bar,
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0x00000000);
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early_read_config_dword(hose, hose->first_busno,
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PCI_FUNC(hose->first_busno), bar,
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&bar_response);
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DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
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hose->first_busno, PCI_SLOT(hose->first_busno),
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PCI_FUNC(hose->first_busno), bar, bar_response);
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}
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/* end work arround */
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}
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void __init
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ep405_map_io(void)
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{
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bd_t *bip = &__res;
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ppc4xx_map_io();
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ep405_bcsr = ioremap(EP405_BCSR_PADDR, EP405_BCSR_SIZE);
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if (bip->bi_nvramsize > 0) {
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ep405_nvram = ioremap(EP405_NVRAM_PADDR, bip->bi_nvramsize);
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}
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}
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void __init
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ep405_init_IRQ(void)
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{
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int i;
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ppc4xx_init_IRQ();
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/* Workaround for a bug in the firmware it incorrectly sets
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the IRQ polarities for XIRQ0 and XIRQ1 */
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mtdcr(DCRN_UIC_PR(DCRN_UIC0_BASE), 0xffffff80); /* set the polarity */
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mtdcr(DCRN_UIC_SR(DCRN_UIC0_BASE), 0x00000060); /* clear bogus interrupts */
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/* Activate the XIRQs from the CPLD */
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writeb(0xf0, ep405_bcsr+10);
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/* Set up IRQ routing */
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for (i = 0; i < ARRAY_SIZE(ep405_devtable); i++) {
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if ( (ep405_devtable[i].irq >= 25)
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&& (ep405_devtable[i].irq) <= 31) {
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writeb(ep405_devtable[i].cpld_xirq_select, ep405_bcsr+5);
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writeb(ep405_devtable[i].irq - 25, ep405_bcsr+6);
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}
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}
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}
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void __init
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platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7)
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{
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ppc4xx_init(r3, r4, r5, r6, r7);
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ppc_md.setup_arch = ep405_setup_arch;
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ppc_md.setup_io_mappings = ep405_map_io;
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ppc_md.init_IRQ = ep405_init_IRQ;
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ppc_md.nvram_read_val = todc_direct_read_val;
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ppc_md.nvram_write_val = todc_direct_write_val;
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if (__res.bi_nvramsize == 512*1024) {
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ppc_md.time_init = todc_time_init;
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ppc_md.set_rtc_time = todc_set_rtc_time;
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ppc_md.get_rtc_time = todc_get_rtc_time;
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} else {
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printk("EP405: NVRTC size is not 512k (not a DS1557). Not sure what to do with it\n");
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}
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}
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