251 lines
8.2 KiB
C
251 lines
8.2 KiB
C
#ifndef B43_XMIT_H_
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#define B43_XMIT_H_
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#include "main.h"
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#define _b43_declare_plcp_hdr(size) \
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struct b43_plcp_hdr##size { \
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union { \
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__le32 data; \
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__u8 raw[size]; \
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} __attribute__((__packed__)); \
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} __attribute__((__packed__))
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/* struct b43_plcp_hdr4 */
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_b43_declare_plcp_hdr(4);
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/* struct b43_plcp_hdr6 */
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_b43_declare_plcp_hdr(6);
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#undef _b43_declare_plcp_hdr
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/* TX header for v4 firmware */
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struct b43_txhdr_fw4 {
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__le32 mac_ctl; /* MAC TX control */
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__le16 mac_frame_ctl; /* Copy of the FrameControl field */
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__le16 tx_fes_time_norm; /* TX FES Time Normal */
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__le16 phy_ctl; /* PHY TX control */
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__le16 phy_ctl_0; /* Unused */
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__le16 phy_ctl_1; /* Unused */
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__le16 phy_ctl_rts_0; /* Unused */
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__le16 phy_ctl_rts_1; /* Unused */
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__u8 phy_rate; /* PHY rate */
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__u8 phy_rate_rts; /* PHY rate for RTS/CTS */
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__u8 extra_ft; /* Extra Frame Types */
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__u8 chan_radio_code; /* Channel Radio Code */
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__u8 iv[16]; /* Encryption IV */
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__u8 tx_receiver[6]; /* TX Frame Receiver address */
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__le16 tx_fes_time_fb; /* TX FES Time Fallback */
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struct b43_plcp_hdr6 rts_plcp_fb; /* RTS fallback PLCP */
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__le16 rts_dur_fb; /* RTS fallback duration */
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struct b43_plcp_hdr6 plcp_fb; /* Fallback PLCP */
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__le16 dur_fb; /* Fallback duration */
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__le16 mm_dur_time; /* Unused */
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__le16 mm_dur_time_fb; /* Unused */
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__le32 time_stamp; /* Timestamp */
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PAD_BYTES(2);
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__le16 cookie; /* TX frame cookie */
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__le16 tx_status; /* TX status */
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struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP */
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__u8 rts_frame[16]; /* The RTS frame (if used) */
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PAD_BYTES(2);
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struct b43_plcp_hdr6 plcp; /* Main PLCP */
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} __attribute__ ((__packed__));
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/* MAC TX control */
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#define B43_TX4_MAC_KEYIDX 0x0FF00000 /* Security key index */
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#define B43_TX4_MAC_KEYIDX_SHIFT 20
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#define B43_TX4_MAC_KEYALG 0x00070000 /* Security key algorithm */
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#define B43_TX4_MAC_KEYALG_SHIFT 16
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#define B43_TX4_MAC_LIFETIME 0x00001000
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#define B43_TX4_MAC_FRAMEBURST 0x00000800
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#define B43_TX4_MAC_SENDCTS 0x00000400
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#define B43_TX4_MAC_AMPDU 0x00000300
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#define B43_TX4_MAC_AMPDU_SHIFT 8
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#define B43_TX4_MAC_5GHZ 0x00000080
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#define B43_TX4_MAC_IGNPMQ 0x00000020
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#define B43_TX4_MAC_HWSEQ 0x00000010 /* Use Hardware Sequence Number */
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#define B43_TX4_MAC_STMSDU 0x00000008 /* Start MSDU */
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#define B43_TX4_MAC_SENDRTS 0x00000004
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#define B43_TX4_MAC_LONGFRAME 0x00000002
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#define B43_TX4_MAC_ACK 0x00000001
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/* Extra Frame Types */
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#define B43_TX4_EFT_FBOFDM 0x0001 /* Data frame fallback rate type */
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#define B43_TX4_EFT_RTSOFDM 0x0004 /* RTS/CTS rate type */
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#define B43_TX4_EFT_RTSFBOFDM 0x0010 /* RTS/CTS fallback rate type */
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/* PHY TX control word */
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#define B43_TX4_PHY_OFDM 0x0001 /* Data frame rate type */
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#define B43_TX4_PHY_SHORTPRMBL 0x0010 /* Use short preamble */
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#define B43_TX4_PHY_ANT 0x03C0 /* Antenna selection */
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#define B43_TX4_PHY_ANT0 0x0000 /* Use antenna 0 */
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#define B43_TX4_PHY_ANT1 0x0100 /* Use antenna 1 */
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#define B43_TX4_PHY_ANTLAST 0x0300 /* Use last used antenna */
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void b43_generate_txhdr(struct b43_wldev *dev,
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u8 * txhdr,
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const unsigned char *fragment_data,
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unsigned int fragment_len,
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const struct ieee80211_tx_control *txctl, u16 cookie);
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/* Transmit Status */
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struct b43_txstatus {
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u16 cookie; /* The cookie from the txhdr */
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u16 seq; /* Sequence number */
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u8 phy_stat; /* PHY TX status */
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u8 frame_count; /* Frame transmit count */
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u8 rts_count; /* RTS transmit count */
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u8 supp_reason; /* Suppression reason */
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/* flags */
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u8 pm_indicated; /* PM mode indicated to AP */
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u8 intermediate; /* Intermediate status notification (not final) */
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u8 for_ampdu; /* Status is for an AMPDU (afterburner) */
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u8 acked; /* Wireless ACK received */
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};
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/* txstatus supp_reason values */
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enum {
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B43_TXST_SUPP_NONE, /* Not suppressed */
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B43_TXST_SUPP_PMQ, /* Suppressed due to PMQ entry */
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B43_TXST_SUPP_FLUSH, /* Suppressed due to flush request */
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B43_TXST_SUPP_PREV, /* Previous fragment failed */
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B43_TXST_SUPP_CHAN, /* Channel mismatch */
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B43_TXST_SUPP_LIFE, /* Lifetime expired */
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B43_TXST_SUPP_UNDER, /* Buffer underflow */
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B43_TXST_SUPP_ABNACK, /* Afterburner NACK */
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};
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/* Transmit Status as received through DMA/PIO on old chips */
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struct b43_hwtxstatus {
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PAD_BYTES(4);
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__le16 cookie;
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u8 flags;
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u8 count;
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PAD_BYTES(2);
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__le16 seq;
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u8 phy_stat;
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PAD_BYTES(1);
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} __attribute__ ((__packed__));
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/* Receive header for v4 firmware. */
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struct b43_rxhdr_fw4 {
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__le16 frame_len; /* Frame length */
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PAD_BYTES(2);
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__le16 phy_status0; /* PHY RX Status 0 */
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__u8 jssi; /* PHY RX Status 1: JSSI */
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__u8 sig_qual; /* PHY RX Status 1: Signal Quality */
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__le16 phy_status2; /* PHY RX Status 2 */
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__le16 phy_status3; /* PHY RX Status 3 */
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__le32 mac_status; /* MAC RX status */
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__le16 mac_time;
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__le16 channel;
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} __attribute__ ((__packed__));
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/* PHY RX Status 0 */
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#define B43_RX_PHYST0_GAINCTL 0x4000 /* Gain Control */
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#define B43_RX_PHYST0_PLCPHCF 0x0200
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#define B43_RX_PHYST0_PLCPFV 0x0100
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#define B43_RX_PHYST0_SHORTPRMBL 0x0080 /* Received with Short Preamble */
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#define B43_RX_PHYST0_LCRS 0x0040
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#define B43_RX_PHYST0_ANT 0x0020 /* Antenna */
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#define B43_RX_PHYST0_UNSRATE 0x0010
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#define B43_RX_PHYST0_CLIP 0x000C
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#define B43_RX_PHYST0_CLIP_SHIFT 2
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#define B43_RX_PHYST0_FTYPE 0x0003 /* Frame type */
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#define B43_RX_PHYST0_CCK 0x0000 /* Frame type: CCK */
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#define B43_RX_PHYST0_OFDM 0x0001 /* Frame type: OFDM */
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#define B43_RX_PHYST0_PRE_N 0x0002 /* Pre-standard N-PHY frame */
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#define B43_RX_PHYST0_STD_N 0x0003 /* Standard N-PHY frame */
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/* PHY RX Status 2 */
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#define B43_RX_PHYST2_LNAG 0xC000 /* LNA Gain */
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#define B43_RX_PHYST2_LNAG_SHIFT 14
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#define B43_RX_PHYST2_PNAG 0x3C00 /* PNA Gain */
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#define B43_RX_PHYST2_PNAG_SHIFT 10
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#define B43_RX_PHYST2_FOFF 0x03FF /* F offset */
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/* PHY RX Status 3 */
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#define B43_RX_PHYST3_DIGG 0x1800 /* DIG Gain */
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#define B43_RX_PHYST3_DIGG_SHIFT 11
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#define B43_RX_PHYST3_TRSTATE 0x0400 /* TR state */
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/* MAC RX Status */
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#define B43_RX_MAC_BEACONSENT 0x00008000 /* Beacon send flag */
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#define B43_RX_MAC_KEYIDX 0x000007E0 /* Key index */
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#define B43_RX_MAC_KEYIDX_SHIFT 5
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#define B43_RX_MAC_DECERR 0x00000010 /* Decrypt error */
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#define B43_RX_MAC_DEC 0x00000008 /* Decryption attempted */
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#define B43_RX_MAC_PADDING 0x00000004 /* Pad bytes present */
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#define B43_RX_MAC_RESP 0x00000002 /* Response frame transmitted */
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#define B43_RX_MAC_FCSERR 0x00000001 /* FCS error */
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/* RX channel */
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#define B43_RX_CHAN_GAIN 0xFC00 /* Gain */
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#define B43_RX_CHAN_GAIN_SHIFT 10
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#define B43_RX_CHAN_ID 0x03FC /* Channel ID */
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#define B43_RX_CHAN_ID_SHIFT 2
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#define B43_RX_CHAN_PHYTYPE 0x0003 /* PHY type */
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u8 b43_plcp_get_ratecode_cck(const u8 bitrate);
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u8 b43_plcp_get_ratecode_ofdm(const u8 bitrate);
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void b43_generate_plcp_hdr(struct b43_plcp_hdr4 *plcp,
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const u16 octets, const u8 bitrate);
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void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr);
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void b43_handle_txstatus(struct b43_wldev *dev,
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const struct b43_txstatus *status);
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void b43_handle_hwtxstatus(struct b43_wldev *dev,
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const struct b43_hwtxstatus *hw);
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void b43_tx_suspend(struct b43_wldev *dev);
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void b43_tx_resume(struct b43_wldev *dev);
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#define B43_NR_QOSPARMS 22
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enum {
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B43_QOSPARM_TXOP = 0,
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B43_QOSPARM_CWMIN,
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B43_QOSPARM_CWMAX,
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B43_QOSPARM_CWCUR,
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B43_QOSPARM_AIFS,
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B43_QOSPARM_BSLOTS,
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B43_QOSPARM_REGGAP,
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B43_QOSPARM_STATUS,
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};
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void b43_qos_init(struct b43_wldev *dev);
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/* Helper functions for converting the key-table index from "firmware-format"
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* to "raw-format" and back. The firmware API changed for this at some revision.
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* We need to account for that here. */
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static inline int b43_new_kidx_api(struct b43_wldev *dev)
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{
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/* FIXME: Not sure the change was at rev 351 */
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return (dev->fw.rev >= 351);
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}
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static inline u8 b43_kidx_to_fw(struct b43_wldev *dev, u8 raw_kidx)
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{
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u8 firmware_kidx;
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if (b43_new_kidx_api(dev)) {
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firmware_kidx = raw_kidx;
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} else {
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if (raw_kidx >= 4) /* Is per STA key? */
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firmware_kidx = raw_kidx - 4;
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else
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firmware_kidx = raw_kidx; /* TX default key */
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}
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return firmware_kidx;
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}
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static inline u8 b43_kidx_to_raw(struct b43_wldev *dev, u8 firmware_kidx)
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{
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u8 raw_kidx;
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if (b43_new_kidx_api(dev))
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raw_kidx = firmware_kidx;
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else
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raw_kidx = firmware_kidx + 4; /* RX default keys or per STA keys */
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return raw_kidx;
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}
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#endif /* B43_XMIT_H_ */
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