142 lines
4.0 KiB
C
142 lines
4.0 KiB
C
/*
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* AMD Alchemy Pb1200 Referrence Board
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* Board Registers defines.
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*
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*
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*/
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#ifndef __ASM_PB1200_H
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#define __ASM_PB1200_H
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#include <linux/types.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-au1x00/au1xxx_psc.h>
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#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
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#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
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#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
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#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
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/*
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* SPI and SMB are muxed on the Pb1200 board.
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* Refer to board documentation.
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*/
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#define SPI_PSC_BASE PSC0_BASE_ADDR
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#define SMBUS_PSC_BASE PSC0_BASE_ADDR
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/*
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* AC97 and I2S are muxed on the Pb1200 board.
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* Refer to board documentation.
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*/
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#define AC97_PSC_BASE PSC1_BASE_ADDR
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#define I2S_PSC_BASE PSC1_BASE_ADDR
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#define BCSR_SYSTEM_VDDI 0x001F
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#define BCSR_SYSTEM_POWEROFF 0x4000
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#define BCSR_SYSTEM_RESET 0x8000
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/* Bit positions for the different interrupt sources */
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#define BCSR_INT_IDE 0x0001
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#define BCSR_INT_ETH 0x0002
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#define BCSR_INT_PC0 0x0004
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#define BCSR_INT_PC0STSCHG 0x0008
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#define BCSR_INT_PC1 0x0010
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#define BCSR_INT_PC1STSCHG 0x0020
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#define BCSR_INT_DC 0x0040
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#define BCSR_INT_FLASHBUSY 0x0080
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#define BCSR_INT_PC0INSERT 0x0100
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#define BCSR_INT_PC0EJECT 0x0200
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#define BCSR_INT_PC1INSERT 0x0400
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#define BCSR_INT_PC1EJECT 0x0800
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#define BCSR_INT_SD0INSERT 0x1000
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#define BCSR_INT_SD0EJECT 0x2000
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#define BCSR_INT_SD1INSERT 0x4000
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#define BCSR_INT_SD1EJECT 0x8000
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#define SMC91C111_PHYS_ADDR 0x0D000300
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#define SMC91C111_INT PB1200_ETH_INT
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#define IDE_PHYS_ADDR 0x0C800000
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#define IDE_REG_SHIFT 5
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#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
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#define IDE_INT PB1200_IDE_INT
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#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
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#define IDE_RQSIZE 128
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#define NAND_PHYS_ADDR 0x1C000000
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/*
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* Timing values as described in databook, * ns value stripped of
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* lower 2 bits.
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* These defines are here rather than an Au1200 generic file because
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* the parts chosen on another board may be different and may require
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* different timings.
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*/
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#define NAND_T_H (18 >> 2)
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#define NAND_T_PUL (30 >> 2)
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#define NAND_T_SU (30 >> 2)
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#define NAND_T_WH (30 >> 2)
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/* Bitfield shift amounts */
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#define NAND_T_H_SHIFT 0
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#define NAND_T_PUL_SHIFT 4
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#define NAND_T_SU_SHIFT 8
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#define NAND_T_WH_SHIFT 12
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#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
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((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
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((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
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((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
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/*
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* External Interrupts for Pb1200 as of 8/6/2004.
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* Bit positions in the CPLD registers can be calculated by taking
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* the interrupt define and subtracting the PB1200_INT_BEGIN value.
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*
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* Example: IDE bis pos is = 64 - 64
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* ETH bit pos is = 65 - 64
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*/
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enum external_pb1200_ints {
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PB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
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PB1200_IDE_INT = PB1200_INT_BEGIN,
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PB1200_ETH_INT,
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PB1200_PC0_INT,
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PB1200_PC0_STSCHG_INT,
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PB1200_PC1_INT,
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PB1200_PC1_STSCHG_INT,
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PB1200_DC_INT,
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PB1200_FLASHBUSY_INT,
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PB1200_PC0_INSERT_INT,
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PB1200_PC0_EJECT_INT,
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PB1200_PC1_INSERT_INT,
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PB1200_PC1_EJECT_INT,
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PB1200_SD0_INSERT_INT,
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PB1200_SD0_EJECT_INT,
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PB1200_SD1_INSERT_INT,
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PB1200_SD1_EJECT_INT,
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PB1200_INT_END = PB1200_INT_BEGIN + 15
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};
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/* NAND chip select */
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#define NAND_CS 1
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#endif /* __ASM_PB1200_H */
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