273 lines
7.1 KiB
C
273 lines
7.1 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* arch/sh64/kernel/irq_intc.c
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*
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* Copyright (C) 2000, 2001 Paolo Alberelli
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* Copyright (C) 2003 Paul Mundt
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*
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* Interrupt Controller support for SH5 INTC.
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* Per-interrupt selective. IRLM=0 (Fixed priority) is not
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* supported being useless without a cascaded interrupt
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* controller.
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*
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/stddef.h>
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#include <linux/bitops.h> /* this includes also <asm/registers.h */
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/* which is required to remap register */
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/* names used into __asm__ blocks... */
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#include <asm/hardware.h>
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#include <asm/platform.h>
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#include <asm/page.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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/*
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* Maybe the generic Peripheral block could move to a more
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* generic include file. INTC Block will be defined here
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* and only here to make INTC self-contained in a single
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* file.
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*/
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#define INTC_BLOCK_OFFSET 0x01000000
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/* Base */
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#define INTC_BASE PHYS_PERIPHERAL_BLOCK + \
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INTC_BLOCK_OFFSET
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/* Address */
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#define INTC_ICR_SET (intc_virt + 0x0)
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#define INTC_ICR_CLEAR (intc_virt + 0x8)
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#define INTC_INTPRI_0 (intc_virt + 0x10)
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#define INTC_INTSRC_0 (intc_virt + 0x50)
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#define INTC_INTSRC_1 (intc_virt + 0x58)
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#define INTC_INTREQ_0 (intc_virt + 0x60)
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#define INTC_INTREQ_1 (intc_virt + 0x68)
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#define INTC_INTENB_0 (intc_virt + 0x70)
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#define INTC_INTENB_1 (intc_virt + 0x78)
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#define INTC_INTDSB_0 (intc_virt + 0x80)
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#define INTC_INTDSB_1 (intc_virt + 0x88)
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#define INTC_ICR_IRLM 0x1
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#define INTC_INTPRI_PREGS 8 /* 8 Priority Registers */
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#define INTC_INTPRI_PPREG 8 /* 8 Priorities per Register */
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/*
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* Mapper between the vector ordinal and the IRQ number
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* passed to kernel/device drivers.
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*/
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int intc_evt_to_irq[(0xE20/0x20)+1] = {
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-1, -1, -1, -1, -1, -1, -1, -1, /* 0x000 - 0x0E0 */
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-1, -1, -1, -1, -1, -1, -1, -1, /* 0x100 - 0x1E0 */
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0, 0, 0, 0, 0, 1, 0, 0, /* 0x200 - 0x2E0 */
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2, 0, 0, 3, 0, 0, 0, -1, /* 0x300 - 0x3E0 */
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32, 33, 34, 35, 36, 37, 38, -1, /* 0x400 - 0x4E0 */
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-1, -1, -1, 63, -1, -1, -1, -1, /* 0x500 - 0x5E0 */
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-1, -1, 18, 19, 20, 21, 22, -1, /* 0x600 - 0x6E0 */
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39, 40, 41, 42, -1, -1, -1, -1, /* 0x700 - 0x7E0 */
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4, 5, 6, 7, -1, -1, -1, -1, /* 0x800 - 0x8E0 */
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-1, -1, -1, -1, -1, -1, -1, -1, /* 0x900 - 0x9E0 */
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12, 13, 14, 15, 16, 17, -1, -1, /* 0xA00 - 0xAE0 */
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-1, -1, -1, -1, -1, -1, -1, -1, /* 0xB00 - 0xBE0 */
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-1, -1, -1, -1, -1, -1, -1, -1, /* 0xC00 - 0xCE0 */
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-1, -1, -1, -1, -1, -1, -1, -1, /* 0xD00 - 0xDE0 */
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-1, -1 /* 0xE00 - 0xE20 */
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};
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/*
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* Opposite mapper.
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*/
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static int IRQ_to_vectorN[NR_INTC_IRQS] = {
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0x12, 0x15, 0x18, 0x1B, 0x40, 0x41, 0x42, 0x43, /* 0- 7 */
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-1, -1, -1, -1, 0x50, 0x51, 0x52, 0x53, /* 8-15 */
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0x54, 0x55, 0x32, 0x33, 0x34, 0x35, 0x36, -1, /* 16-23 */
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-1, -1, -1, -1, -1, -1, -1, -1, /* 24-31 */
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0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x38, /* 32-39 */
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0x39, 0x3A, 0x3B, -1, -1, -1, -1, -1, /* 40-47 */
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-1, -1, -1, -1, -1, -1, -1, -1, /* 48-55 */
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-1, -1, -1, -1, -1, -1, -1, 0x2B, /* 56-63 */
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};
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static unsigned long intc_virt;
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static unsigned int startup_intc_irq(unsigned int irq);
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static void shutdown_intc_irq(unsigned int irq);
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static void enable_intc_irq(unsigned int irq);
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static void disable_intc_irq(unsigned int irq);
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static void mask_and_ack_intc(unsigned int);
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static void end_intc_irq(unsigned int irq);
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static struct hw_interrupt_type intc_irq_type = {
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"INTC",
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startup_intc_irq,
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shutdown_intc_irq,
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enable_intc_irq,
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disable_intc_irq,
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mask_and_ack_intc,
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end_intc_irq
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};
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static int irlm; /* IRL mode */
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static unsigned int startup_intc_irq(unsigned int irq)
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{
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enable_intc_irq(irq);
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return 0; /* never anything pending */
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}
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static void shutdown_intc_irq(unsigned int irq)
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{
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disable_intc_irq(irq);
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}
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static void enable_intc_irq(unsigned int irq)
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{
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unsigned long reg;
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unsigned long bitmask;
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if ((irq <= IRQ_IRL3) && (irlm == NO_PRIORITY))
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printk("Trying to use straight IRL0-3 with an encoding platform.\n");
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if (irq < 32) {
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reg = INTC_INTENB_0;
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bitmask = 1 << irq;
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} else {
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reg = INTC_INTENB_1;
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bitmask = 1 << (irq - 32);
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}
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ctrl_outl(bitmask, reg);
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}
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static void disable_intc_irq(unsigned int irq)
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{
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unsigned long reg;
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unsigned long bitmask;
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if (irq < 32) {
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reg = INTC_INTDSB_0;
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bitmask = 1 << irq;
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} else {
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reg = INTC_INTDSB_1;
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bitmask = 1 << (irq - 32);
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}
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ctrl_outl(bitmask, reg);
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}
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static void mask_and_ack_intc(unsigned int irq)
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{
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disable_intc_irq(irq);
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}
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static void end_intc_irq(unsigned int irq)
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{
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enable_intc_irq(irq);
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}
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/* For future use, if we ever support IRLM=0) */
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void make_intc_irq(unsigned int irq)
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{
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disable_irq_nosync(irq);
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irq_desc[irq].handler = &intc_irq_type;
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disable_intc_irq(irq);
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}
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#if defined(CONFIG_PROC_FS) && defined(CONFIG_SYSCTL)
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int intc_irq_describe(char* p, int irq)
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{
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if (irq < NR_INTC_IRQS)
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return sprintf(p, "(0x%3x)", IRQ_to_vectorN[irq]*0x20);
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else
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return 0;
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}
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#endif
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void __init init_IRQ(void)
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{
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unsigned long long __dummy0, __dummy1=~0x00000000100000f0;
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unsigned long reg;
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unsigned long data;
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int i;
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intc_virt = onchip_remap(INTC_BASE, 1024, "INTC");
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if (!intc_virt) {
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panic("Unable to remap INTC\n");
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}
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/* Set default: per-line enable/disable, priority driven ack/eoi */
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for (i = 0; i < NR_INTC_IRQS; i++) {
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if (platform_int_priority[i] != NO_PRIORITY) {
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irq_desc[i].handler = &intc_irq_type;
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}
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}
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/* Disable all interrupts and set all priorities to 0 to avoid trouble */
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ctrl_outl(-1, INTC_INTDSB_0);
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ctrl_outl(-1, INTC_INTDSB_1);
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for (reg = INTC_INTPRI_0, i = 0; i < INTC_INTPRI_PREGS; i++, reg += 8)
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ctrl_outl( NO_PRIORITY, reg);
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/* Set IRLM */
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/* If all the priorities are set to 'no priority', then
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* assume we are using encoded mode.
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*/
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irlm = platform_int_priority[IRQ_IRL0] + platform_int_priority[IRQ_IRL1] + \
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platform_int_priority[IRQ_IRL2] + platform_int_priority[IRQ_IRL3];
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if (irlm == NO_PRIORITY) {
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/* IRLM = 0 */
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reg = INTC_ICR_CLEAR;
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i = IRQ_INTA;
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printk("Trying to use encoded IRL0-3. IRLs unsupported.\n");
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} else {
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/* IRLM = 1 */
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reg = INTC_ICR_SET;
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i = IRQ_IRL0;
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}
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ctrl_outl(INTC_ICR_IRLM, reg);
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/* Set interrupt priorities according to platform description */
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for (data = 0, reg = INTC_INTPRI_0; i < NR_INTC_IRQS; i++) {
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data |= platform_int_priority[i] << ((i % INTC_INTPRI_PPREG) * 4);
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if ((i % INTC_INTPRI_PPREG) == (INTC_INTPRI_PPREG - 1)) {
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/* Upon the 7th, set Priority Register */
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ctrl_outl(data, reg);
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data = 0;
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reg += 8;
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}
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}
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#ifdef CONFIG_SH_CAYMAN
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{
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extern void init_cayman_irq(void);
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init_cayman_irq();
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}
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#endif
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/*
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* And now let interrupts come in.
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* sti() is not enough, we need to
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* lower priority, too.
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*/
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__asm__ __volatile__("getcon " __SR ", %0\n\t"
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"and %0, %1, %0\n\t"
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"putcon %0, " __SR "\n\t"
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: "=&r" (__dummy0)
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: "r" (__dummy1));
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}
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