166 lines
4.0 KiB
C
166 lines
4.0 KiB
C
/* 32 and 64-bit millicode, original author Hewlett-Packard
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adapted for gcc by Paul Bame <bame@debian.org>
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and Alan Modra <alan@linuxcare.com.au>.
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Copyright 2001, 2002, 2003 Free Software Foundation, Inc.
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This file is part of GCC and is released under the terms of
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of the GNU General Public License as published by the Free Software
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Foundation; either version 2, or (at your option) any later version.
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See the file COPYING in the top-level GCC source directory for a copy
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of the license. */
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#ifndef _PA_MILLI_H_
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#define _PA_MILLI_H_
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#define L_dyncall
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#define L_divI
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#define L_divU
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#define L_remI
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#define L_remU
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#define L_div_const
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#define L_mulI
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#ifdef CONFIG_64BIT
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.level 2.0w
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#endif
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/* Hardware General Registers. */
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r0: .reg %r0
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r1: .reg %r1
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r2: .reg %r2
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r3: .reg %r3
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r4: .reg %r4
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r5: .reg %r5
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r6: .reg %r6
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r7: .reg %r7
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r8: .reg %r8
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r9: .reg %r9
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r10: .reg %r10
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r11: .reg %r11
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r12: .reg %r12
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r13: .reg %r13
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r14: .reg %r14
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r15: .reg %r15
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r16: .reg %r16
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r17: .reg %r17
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r18: .reg %r18
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r19: .reg %r19
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r20: .reg %r20
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r21: .reg %r21
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r22: .reg %r22
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r23: .reg %r23
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r24: .reg %r24
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r25: .reg %r25
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r26: .reg %r26
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r27: .reg %r27
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r28: .reg %r28
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r29: .reg %r29
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r30: .reg %r30
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r31: .reg %r31
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/* Hardware Space Registers. */
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sr0: .reg %sr0
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sr1: .reg %sr1
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sr2: .reg %sr2
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sr3: .reg %sr3
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sr4: .reg %sr4
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sr5: .reg %sr5
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sr6: .reg %sr6
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sr7: .reg %sr7
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/* Hardware Floating Point Registers. */
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fr0: .reg %fr0
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fr1: .reg %fr1
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fr2: .reg %fr2
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fr3: .reg %fr3
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fr4: .reg %fr4
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fr5: .reg %fr5
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fr6: .reg %fr6
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fr7: .reg %fr7
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fr8: .reg %fr8
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fr9: .reg %fr9
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fr10: .reg %fr10
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fr11: .reg %fr11
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fr12: .reg %fr12
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fr13: .reg %fr13
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fr14: .reg %fr14
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fr15: .reg %fr15
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/* Hardware Control Registers. */
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cr11: .reg %cr11
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sar: .reg %cr11 /* Shift Amount Register */
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/* Software Architecture General Registers. */
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rp: .reg r2 /* return pointer */
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#ifdef CONFIG_64BIT
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mrp: .reg r2 /* millicode return pointer */
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#else
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mrp: .reg r31 /* millicode return pointer */
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#endif
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ret0: .reg r28 /* return value */
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ret1: .reg r29 /* return value (high part of double) */
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sp: .reg r30 /* stack pointer */
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dp: .reg r27 /* data pointer */
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arg0: .reg r26 /* argument */
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arg1: .reg r25 /* argument or high part of double argument */
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arg2: .reg r24 /* argument */
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arg3: .reg r23 /* argument or high part of double argument */
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/* Software Architecture Space Registers. */
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/* sr0 ; return link from BLE */
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sret: .reg sr1 /* return value */
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sarg: .reg sr1 /* argument */
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/* sr4 ; PC SPACE tracker */
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/* sr5 ; process private data */
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/* Frame Offsets (millicode convention!) Used when calling other
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millicode routines. Stack unwinding is dependent upon these
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definitions. */
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r31_slot: .equ -20 /* "current RP" slot */
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sr0_slot: .equ -16 /* "static link" slot */
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#if defined(CONFIG_64BIT)
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mrp_slot: .equ -16 /* "current RP" slot */
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psp_slot: .equ -8 /* "previous SP" slot */
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#else
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mrp_slot: .equ -20 /* "current RP" slot (replacing "r31_slot") */
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#endif
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#define DEFINE(name,value)name: .EQU value
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#define RDEFINE(name,value)name: .REG value
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#ifdef milliext
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#define MILLI_BE(lbl) BE lbl(sr7,r0)
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#define MILLI_BEN(lbl) BE,n lbl(sr7,r0)
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#define MILLI_BLE(lbl) BLE lbl(sr7,r0)
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#define MILLI_BLEN(lbl) BLE,n lbl(sr7,r0)
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#define MILLIRETN BE,n 0(sr0,mrp)
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#define MILLIRET BE 0(sr0,mrp)
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#define MILLI_RETN BE,n 0(sr0,mrp)
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#define MILLI_RET BE 0(sr0,mrp)
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#else
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#define MILLI_BE(lbl) B lbl
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#define MILLI_BEN(lbl) B,n lbl
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#define MILLI_BLE(lbl) BL lbl,mrp
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#define MILLI_BLEN(lbl) BL,n lbl,mrp
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#define MILLIRETN BV,n 0(mrp)
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#define MILLIRET BV 0(mrp)
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#define MILLI_RETN BV,n 0(mrp)
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#define MILLI_RET BV 0(mrp)
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#endif
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#define CAT(a,b) a##b
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#define SUBSPA_MILLI .section .text
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#define SUBSPA_MILLI_DIV .section .text.div,"ax",@progbits! .align 16
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#define SUBSPA_MILLI_MUL .section .text.mul,"ax",@progbits! .align 16
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#define ATTR_MILLI
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#define SUBSPA_DATA .section .data
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#define ATTR_DATA
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#define GLOBAL $global$
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#define GSYM(sym) !sym:
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#define LSYM(sym) !CAT(.L,sym:)
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#define LREF(sym) CAT(.L,sym)
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#endif /*_PA_MILLI_H_*/
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