242 lines
7.9 KiB
C
242 lines
7.9 KiB
C
/*
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* Copyright (C) 2005 Silicon Graphics, Inc.
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*/
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#ifndef IA64_SN_IOC3_H
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#define IA64_SN_IOC3_H
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/* serial port register map */
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struct ioc3_serialregs {
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uint32_t sscr;
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uint32_t stpir;
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uint32_t stcir;
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uint32_t srpir;
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uint32_t srcir;
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uint32_t srtr;
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uint32_t shadow;
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};
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/* SUPERIO uart register map */
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struct ioc3_uartregs {
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char iu_lcr;
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union {
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char iir; /* read only */
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char fcr; /* write only */
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} u3;
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union {
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char ier; /* DLAB == 0 */
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char dlm; /* DLAB == 1 */
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} u2;
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union {
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char rbr; /* read only, DLAB == 0 */
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char thr; /* write only, DLAB == 0 */
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char dll; /* DLAB == 1 */
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} u1;
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char iu_scr;
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char iu_msr;
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char iu_lsr;
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char iu_mcr;
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};
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#define iu_rbr u1.rbr
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#define iu_thr u1.thr
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#define iu_dll u1.dll
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#define iu_ier u2.ier
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#define iu_dlm u2.dlm
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#define iu_iir u3.iir
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#define iu_fcr u3.fcr
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struct ioc3_sioregs {
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char fill[0x170];
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struct ioc3_uartregs uartb;
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struct ioc3_uartregs uarta;
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};
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/* PCI IO/mem space register map */
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struct ioc3 {
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uint32_t pci_id;
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uint32_t pci_scr;
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uint32_t pci_rev;
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uint32_t pci_lat;
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uint32_t pci_addr;
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uint32_t pci_err_addr_l;
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uint32_t pci_err_addr_h;
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uint32_t sio_ir;
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/* these registers are read-only for general kernel code. To
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* modify them use the functions in ioc3.c
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*/
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uint32_t sio_ies;
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uint32_t sio_iec;
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uint32_t sio_cr;
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uint32_t int_out;
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uint32_t mcr;
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uint32_t gpcr_s;
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uint32_t gpcr_c;
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uint32_t gpdr;
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uint32_t gppr[9];
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char fill[0x4c];
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/* serial port registers */
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uint32_t sbbr_h;
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uint32_t sbbr_l;
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struct ioc3_serialregs port_a;
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struct ioc3_serialregs port_b;
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char fill1[0x1ff10];
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/* superio registers */
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struct ioc3_sioregs sregs;
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};
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/* These don't exist on the ioc3 serial card... */
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#define eier fill1[8]
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#define eisr fill1[4]
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#define PCI_LAT 0xc /* Latency Timer */
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#define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */
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#define UARTA_BASE 0x178
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#define UARTB_BASE 0x170
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/* bitmasks for serial RX status byte */
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#define RXSB_OVERRUN 0x01 /* char(s) lost */
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#define RXSB_PAR_ERR 0x02 /* parity error */
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#define RXSB_FRAME_ERR 0x04 /* framing error */
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#define RXSB_BREAK 0x08 /* break character */
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#define RXSB_CTS 0x10 /* state of CTS */
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#define RXSB_DCD 0x20 /* state of DCD */
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#define RXSB_MODEM_VALID 0x40 /* DCD, CTS and OVERRUN are valid */
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#define RXSB_DATA_VALID 0x80 /* FRAME_ERR PAR_ERR & BREAK valid */
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/* bitmasks for serial TX control byte */
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#define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */
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#define TXCB_INVALID 0x00 /* byte is invalid */
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#define TXCB_VALID 0x40 /* byte is valid */
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#define TXCB_MCR 0x80 /* data<7:0> to modem cntrl register */
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#define TXCB_DELAY 0xc0 /* delay data<7:0> mSec */
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/* bitmasks for SBBR_L */
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#define SBBR_L_SIZE 0x00000001 /* 0 1KB rings, 1 4KB rings */
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/* bitmasks for SSCR_<A:B> */
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#define SSCR_RX_THRESHOLD 0x000001ff /* hiwater mark */
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#define SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */
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#define SSCR_HFC_EN 0x00020000 /* h/w flow cntrl enabled */
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#define SSCR_RX_RING_DCD 0x00040000 /* postRX record on delta-DCD */
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#define SSCR_RX_RING_CTS 0x00080000 /* postRX record on delta-CTS */
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#define SSCR_HIGH_SPD 0x00100000 /* 4X speed */
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#define SSCR_DIAG 0x00200000 /* bypass clock divider */
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#define SSCR_RX_DRAIN 0x08000000 /* drain RX buffer to memory */
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#define SSCR_DMA_EN 0x10000000 /* enable ring buffer DMA */
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#define SSCR_DMA_PAUSE 0x20000000 /* pause DMA */
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#define SSCR_PAUSE_STATE 0x40000000 /* set when PAUSE takes effect*/
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#define SSCR_RESET 0x80000000 /* reset DMA channels */
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/* all producer/comsumer pointers are the same bitfield */
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#define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */
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#define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */
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#define PROD_CONS_PTR_OFF 3
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/* bitmasks for SRCIR_<A:B> */
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#define SRCIR_ARM 0x80000000 /* arm RX timer */
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/* bitmasks for SHADOW_<A:B> */
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#define SHADOW_DR 0x00000001 /* data ready */
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#define SHADOW_OE 0x00000002 /* overrun error */
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#define SHADOW_PE 0x00000004 /* parity error */
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#define SHADOW_FE 0x00000008 /* framing error */
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#define SHADOW_BI 0x00000010 /* break interrupt */
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#define SHADOW_THRE 0x00000020 /* transmit holding reg empty */
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#define SHADOW_TEMT 0x00000040 /* transmit shift reg empty */
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#define SHADOW_RFCE 0x00000080 /* char in RX fifo has error */
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#define SHADOW_DCTS 0x00010000 /* delta clear to send */
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#define SHADOW_DDCD 0x00080000 /* delta data carrier detect */
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#define SHADOW_CTS 0x00100000 /* clear to send */
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#define SHADOW_DCD 0x00800000 /* data carrier detect */
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#define SHADOW_DTR 0x01000000 /* data terminal ready */
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#define SHADOW_RTS 0x02000000 /* request to send */
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#define SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */
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#define SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */
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#define SHADOW_LOOP 0x10000000 /* loopback enabled */
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/* bitmasks for SRTR_<A:B> */
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#define SRTR_CNT 0x00000fff /* reload value for RX timer */
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#define SRTR_CNT_VAL 0x0fff0000 /* current value of RX timer */
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#define SRTR_CNT_VAL_SHIFT 16
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#define SRTR_HZ 16000 /* SRTR clock frequency */
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/* bitmasks for SIO_IR, SIO_IEC and SIO_IES */
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#define SIO_IR_SA_TX_MT 0x00000001 /* Serial port A TX empty */
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#define SIO_IR_SA_RX_FULL 0x00000002 /* port A RX buf full */
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#define SIO_IR_SA_RX_HIGH 0x00000004 /* port A RX hiwat */
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#define SIO_IR_SA_RX_TIMER 0x00000008 /* port A RX timeout */
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#define SIO_IR_SA_DELTA_DCD 0x00000010 /* port A delta DCD */
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#define SIO_IR_SA_DELTA_CTS 0x00000020 /* port A delta CTS */
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#define SIO_IR_SA_INT 0x00000040 /* port A pass-thru intr */
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#define SIO_IR_SA_TX_EXPLICIT 0x00000080 /* port A explicit TX thru */
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#define SIO_IR_SA_MEMERR 0x00000100 /* port A PCI error */
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#define SIO_IR_SB_TX_MT 0x00000200
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#define SIO_IR_SB_RX_FULL 0x00000400
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#define SIO_IR_SB_RX_HIGH 0x00000800
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#define SIO_IR_SB_RX_TIMER 0x00001000
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#define SIO_IR_SB_DELTA_DCD 0x00002000
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#define SIO_IR_SB_DELTA_CTS 0x00004000
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#define SIO_IR_SB_INT 0x00008000
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#define SIO_IR_SB_TX_EXPLICIT 0x00010000
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#define SIO_IR_SB_MEMERR 0x00020000
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#define SIO_IR_PP_INT 0x00040000 /* P port pass-thru intr */
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#define SIO_IR_PP_INTA 0x00080000 /* PP context A thru */
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#define SIO_IR_PP_INTB 0x00100000 /* PP context B thru */
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#define SIO_IR_PP_MEMERR 0x00200000 /* PP PCI error */
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#define SIO_IR_KBD_INT 0x00400000 /* kbd/mouse intr */
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#define SIO_IR_RT_INT 0x08000000 /* RT output pulse */
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#define SIO_IR_GEN_INT1 0x10000000 /* RT input pulse */
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#define SIO_IR_GEN_INT_SHIFT 28
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/* per device interrupt masks */
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#define SIO_IR_SA (SIO_IR_SA_TX_MT | \
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SIO_IR_SA_RX_FULL | \
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SIO_IR_SA_RX_HIGH | \
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SIO_IR_SA_RX_TIMER | \
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SIO_IR_SA_DELTA_DCD | \
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SIO_IR_SA_DELTA_CTS | \
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SIO_IR_SA_INT | \
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SIO_IR_SA_TX_EXPLICIT | \
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SIO_IR_SA_MEMERR)
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#define SIO_IR_SB (SIO_IR_SB_TX_MT | \
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SIO_IR_SB_RX_FULL | \
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SIO_IR_SB_RX_HIGH | \
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SIO_IR_SB_RX_TIMER | \
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SIO_IR_SB_DELTA_DCD | \
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SIO_IR_SB_DELTA_CTS | \
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SIO_IR_SB_INT | \
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SIO_IR_SB_TX_EXPLICIT | \
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SIO_IR_SB_MEMERR)
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#define SIO_IR_PP (SIO_IR_PP_INT | SIO_IR_PP_INTA | \
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SIO_IR_PP_INTB | SIO_IR_PP_MEMERR)
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#define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1)
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/* bitmasks for SIO_CR */
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#define SIO_CR_CMD_PULSE_SHIFT 15
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#define SIO_CR_SER_A_BASE_SHIFT 1
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#define SIO_CR_SER_B_BASE_SHIFT 8
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#define SIO_CR_ARB_DIAG 0x00380000 /* cur !enet PCI requet (ro) */
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#define SIO_CR_ARB_DIAG_TXA 0x00000000
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#define SIO_CR_ARB_DIAG_RXA 0x00080000
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#define SIO_CR_ARB_DIAG_TXB 0x00100000
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#define SIO_CR_ARB_DIAG_RXB 0x00180000
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#define SIO_CR_ARB_DIAG_PP 0x00200000
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#define SIO_CR_ARB_DIAG_IDLE 0x00400000 /* 0 -> active request (ro) */
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/* defs for some of the generic I/O pins */
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#define GPCR_PHY_RESET 0x20 /* pin is output to PHY reset */
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#define GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */
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#define GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */
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#define GPPR_PHY_RESET_PIN 5 /* GIO pin controlling phy reset */
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#define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin cntrling uartb modeselect */
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#define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin cntrling uarta modeselect */
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#endif /* IA64_SN_IOC3_H */
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