205 lines
5.1 KiB
C
205 lines
5.1 KiB
C
/* arch/arm/mach-s3c2410/include/mach/dma.h
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*
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* Copyright (C) 2003-2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* Samsung S3C24XX DMA support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_DMA_H
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#define __ASM_ARCH_DMA_H __FILE__
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#include <plat/dma.h>
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#include <linux/sysdev.h>
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#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
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/* We use `virtual` dma channels to hide the fact we have only a limited
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* number of DMA channels, and not of all of them (dependant on the device)
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* can be attached to any DMA source. We therefore let the DMA core handle
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* the allocation of hardware channels to clients.
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*/
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enum dma_ch {
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DMACH_XD0,
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DMACH_XD1,
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DMACH_SDI,
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DMACH_SPI0,
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DMACH_SPI1,
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DMACH_UART0,
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DMACH_UART1,
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DMACH_UART2,
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DMACH_TIMER,
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DMACH_I2S_IN,
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DMACH_I2S_OUT,
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DMACH_PCM_IN,
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DMACH_PCM_OUT,
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DMACH_MIC_IN,
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DMACH_USB_EP1,
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DMACH_USB_EP2,
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DMACH_USB_EP3,
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DMACH_USB_EP4,
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DMACH_UART0_SRC2, /* s3c2412 second uart sources */
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DMACH_UART1_SRC2,
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DMACH_UART2_SRC2,
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DMACH_UART3, /* s3c2443 has extra uart */
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DMACH_UART3_SRC2,
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DMACH_MAX, /* the end entry */
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};
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#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
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/* we have 4 dma channels */
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#ifndef CONFIG_CPU_S3C2443
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#define S3C_DMA_CHANNELS (4)
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#else
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#define S3C_DMA_CHANNELS (6)
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#endif
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/* types */
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enum s3c2410_dma_state {
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S3C2410_DMA_IDLE,
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S3C2410_DMA_RUNNING,
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S3C2410_DMA_PAUSED
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};
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/* enum s3c2410_dma_loadst
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*
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* This represents the state of the DMA engine, wrt to the loaded / running
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* transfers. Since we don't have any way of knowing exactly the state of
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* the DMA transfers, we need to know the state to make decisions on wether
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* we can
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*
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* S3C2410_DMA_NONE
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*
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* There are no buffers loaded (the channel should be inactive)
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*
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* S3C2410_DMA_1LOADED
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*
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* There is one buffer loaded, however it has not been confirmed to be
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* loaded by the DMA engine. This may be because the channel is not
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* yet running, or the DMA driver decided that it was too costly to
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* sit and wait for it to happen.
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*
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* S3C2410_DMA_1RUNNING
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*
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* The buffer has been confirmed running, and not finisged
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*
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* S3C2410_DMA_1LOADED_1RUNNING
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*
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* There is a buffer waiting to be loaded by the DMA engine, and one
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* currently running.
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*/
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enum s3c2410_dma_loadst {
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S3C2410_DMALOAD_NONE,
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S3C2410_DMALOAD_1LOADED,
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S3C2410_DMALOAD_1RUNNING,
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S3C2410_DMALOAD_1LOADED_1RUNNING,
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};
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/* flags */
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#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about
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* waiting for reloads */
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#define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */
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#define S3C2410_DMAF_CIRCULAR (1 << 2) /* no circular dma support */
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/* dma buffer */
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struct s3c2410_dma_buf;
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/* s3c2410_dma_buf
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*
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* internally used buffer structure to describe a queued or running
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* buffer.
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*/
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struct s3c2410_dma_buf {
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struct s3c2410_dma_buf *next;
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int magic; /* magic */
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int size; /* buffer size in bytes */
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dma_addr_t data; /* start of DMA data */
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dma_addr_t ptr; /* where the DMA got to [1] */
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void *id; /* client's id */
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};
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/* [1] is this updated for both recv/send modes? */
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struct s3c2410_dma_stats {
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unsigned long loads;
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unsigned long timeout_longest;
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unsigned long timeout_shortest;
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unsigned long timeout_avg;
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unsigned long timeout_failed;
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};
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struct s3c2410_dma_map;
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/* struct s3c2410_dma_chan
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*
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* full state information for each DMA channel
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*/
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struct s3c2410_dma_chan {
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/* channel state flags and information */
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unsigned char number; /* number of this dma channel */
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unsigned char in_use; /* channel allocated */
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unsigned char irq_claimed; /* irq claimed for channel */
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unsigned char irq_enabled; /* irq enabled for channel */
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unsigned char xfer_unit; /* size of an transfer */
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/* channel state */
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enum s3c2410_dma_state state;
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enum s3c2410_dma_loadst load_state;
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struct s3c2410_dma_client *client;
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/* channel configuration */
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enum s3c2410_dmasrc source;
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enum dma_ch req_ch;
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unsigned long dev_addr;
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unsigned long load_timeout;
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unsigned int flags; /* channel flags */
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struct s3c24xx_dma_map *map; /* channel hw maps */
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/* channel's hardware position and configuration */
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void __iomem *regs; /* channels registers */
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void __iomem *addr_reg; /* data address register */
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unsigned int irq; /* channel irq */
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unsigned long dcon; /* default value of DCON */
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/* driver handles */
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s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
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s3c2410_dma_opfn_t op_fn; /* channel op callback */
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/* stats gathering */
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struct s3c2410_dma_stats *stats;
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struct s3c2410_dma_stats stats_store;
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/* buffer list and information */
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struct s3c2410_dma_buf *curr; /* current dma buffer */
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struct s3c2410_dma_buf *next; /* next buffer to load */
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struct s3c2410_dma_buf *end; /* end of queue */
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/* system device */
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struct sys_device dev;
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};
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typedef unsigned long dma_device_t;
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static inline bool s3c_dma_has_circular(void)
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{
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return false;
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}
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#endif /* __ASM_ARCH_DMA_H */
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