87 lines
3.6 KiB
C
87 lines
3.6 KiB
C
/* MN10300 on-chip Real-Time Clock registers
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#ifndef _ASM_RTC_REGS_H
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#define _ASM_RTC_REGS_H
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#include <asm/intctl-regs.h>
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#ifdef __KERNEL__
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#define RTSCR __SYSREG(0xd8600000, u8) /* RTC seconds count reg */
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#define RTSAR __SYSREG(0xd8600001, u8) /* RTC seconds alarm reg */
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#define RTMCR __SYSREG(0xd8600002, u8) /* RTC minutes count reg */
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#define RTMAR __SYSREG(0xd8600003, u8) /* RTC minutes alarm reg */
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#define RTHCR __SYSREG(0xd8600004, u8) /* RTC hours count reg */
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#define RTHAR __SYSREG(0xd8600005, u8) /* RTC hours alarm reg */
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#define RTDWCR __SYSREG(0xd8600006, u8) /* RTC day of the week count reg */
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#define RTDMCR __SYSREG(0xd8600007, u8) /* RTC days count reg */
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#define RTMTCR __SYSREG(0xd8600008, u8) /* RTC months count reg */
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#define RTYCR __SYSREG(0xd8600009, u8) /* RTC years count reg */
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#define RTCRA __SYSREG(0xd860000a, u8)/* RTC control reg A */
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#define RTCRA_RS 0x0f /* periodic timer interrupt cycle setting */
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#define RTCRA_RS_NONE 0x00 /* - off */
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#define RTCRA_RS_3_90625ms 0x01 /* - 3.90625ms (1/256s) */
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#define RTCRA_RS_7_8125ms 0x02 /* - 7.8125ms (1/128s) */
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#define RTCRA_RS_122_070us 0x03 /* - 122.070us (1/8192s) */
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#define RTCRA_RS_244_141us 0x04 /* - 244.141us (1/4096s) */
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#define RTCRA_RS_488_281us 0x05 /* - 488.281us (1/2048s) */
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#define RTCRA_RS_976_5625us 0x06 /* - 976.5625us (1/1024s) */
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#define RTCRA_RS_1_953125ms 0x07 /* - 1.953125ms (1/512s) */
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#define RTCRA_RS_3_90624ms 0x08 /* - 3.90624ms (1/256s) */
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#define RTCRA_RS_7_8125ms_b 0x09 /* - 7.8125ms (1/128s) */
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#define RTCRA_RS_15_625ms 0x0a /* - 15.625ms (1/64s) */
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#define RTCRA_RS_31_25ms 0x0b /* - 31.25ms (1/32s) */
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#define RTCRA_RS_62_5ms 0x0c /* - 62.5ms (1/16s) */
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#define RTCRA_RS_125ms 0x0d /* - 125ms (1/8s) */
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#define RTCRA_RS_250ms 0x0e /* - 250ms (1/4s) */
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#define RTCRA_RS_500ms 0x0f /* - 500ms (1/2s) */
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#define RTCRA_DVR 0x40 /* divider reset */
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#define RTCRA_UIP 0x80 /* clock update flag */
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#define RTCRB __SYSREG(0xd860000b, u8) /* RTC control reg B */
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#define RTCRB_DSE 0x01 /* daylight savings time enable */
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#define RTCRB_TM 0x02 /* time format */
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#define RTCRB_TM_12HR 0x00 /* - 12 hour format */
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#define RTCRB_TM_24HR 0x02 /* - 24 hour format */
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#define RTCRB_DM 0x04 /* numeric value format */
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#define RTCRB_DM_BCD 0x00 /* - BCD */
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#define RTCRB_DM_BINARY 0x04 /* - binary */
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#define RTCRB_UIE 0x10 /* update interrupt disable */
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#define RTCRB_AIE 0x20 /* alarm interrupt disable */
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#define RTCRB_PIE 0x40 /* periodic interrupt disable */
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#define RTCRB_SET 0x80 /* clock update enable */
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#define RTSRC __SYSREG(0xd860000c, u8) /* RTC status reg C */
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#define RTSRC_UF 0x10 /* update end interrupt flag */
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#define RTSRC_AF 0x20 /* alarm interrupt flag */
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#define RTSRC_PF 0x40 /* periodic interrupt flag */
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#define RTSRC_IRQF 0x80 /* interrupt flag */
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#define RTIRQ 32
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#define RTICR GxICR(RTIRQ)
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/*
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* MC146818 RTC compatibility defs for the MN10300 on-chip RTC
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*/
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#define RTC_PORT(x) 0xd8600000
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#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */
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#define CMOS_READ(addr) __SYSREG(0xd8600000 + (addr), u8)
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#define CMOS_WRITE(val, addr) \
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do { __SYSREG(0xd8600000 + (addr), u8) = val; } while (0)
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#define RTC_IRQ RTIRQ
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#endif /* __KERNEL__ */
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#endif /* _ASM_RTC_REGS_H */
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