251 lines
5.4 KiB
C
251 lines
5.4 KiB
C
#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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#include <asm/atomic.h>
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#include <asm/rwlock.h>
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#include <asm/page.h>
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#include <linux/config.h>
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#include <linux/compiler.h>
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asmlinkage int printk(const char * fmt, ...)
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__attribute__ ((format (printf, 1, 2)));
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/*
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* Your basic SMP spinlocks, allowing only a single CPU anywhere
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*/
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typedef struct {
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volatile unsigned int slock;
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#ifdef CONFIG_DEBUG_SPINLOCK
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unsigned magic;
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#endif
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#ifdef CONFIG_PREEMPT
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unsigned int break_lock;
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#endif
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} spinlock_t;
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#define SPINLOCK_MAGIC 0xdead4ead
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#ifdef CONFIG_DEBUG_SPINLOCK
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#define SPINLOCK_MAGIC_INIT , SPINLOCK_MAGIC
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#else
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#define SPINLOCK_MAGIC_INIT /* */
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#endif
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#define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 SPINLOCK_MAGIC_INIT }
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#define spin_lock_init(x) do { *(x) = SPIN_LOCK_UNLOCKED; } while(0)
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/*
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* Simple spin lock operations. There are two variants, one clears IRQ's
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* on the local processor, one does not.
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*
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* We make no fairness assumptions. They have a cost.
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*/
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#define spin_is_locked(x) (*(volatile signed char *)(&(x)->slock) <= 0)
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#define spin_unlock_wait(x) do { barrier(); } while(spin_is_locked(x))
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#define spin_lock_string \
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"\n1:\t" \
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"lock ; decb %0\n\t" \
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"jns 3f\n" \
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"2:\t" \
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"rep;nop\n\t" \
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"cmpb $0,%0\n\t" \
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"jle 2b\n\t" \
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"jmp 1b\n" \
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"3:\n\t"
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#define spin_lock_string_flags \
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"\n1:\t" \
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"lock ; decb %0\n\t" \
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"jns 4f\n\t" \
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"2:\t" \
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"testl $0x200, %1\n\t" \
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"jz 3f\n\t" \
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"sti\n\t" \
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"3:\t" \
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"rep;nop\n\t" \
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"cmpb $0, %0\n\t" \
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"jle 3b\n\t" \
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"cli\n\t" \
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"jmp 1b\n" \
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"4:\n\t"
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/*
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* This works. Despite all the confusion.
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* (except on PPro SMP or if we are using OOSTORE)
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* (PPro errata 66, 92)
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*/
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#if !defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE)
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#define spin_unlock_string \
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"movb $1,%0" \
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:"=m" (lock->slock) : : "memory"
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static inline void _raw_spin_unlock(spinlock_t *lock)
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{
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#ifdef CONFIG_DEBUG_SPINLOCK
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BUG_ON(lock->magic != SPINLOCK_MAGIC);
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BUG_ON(!spin_is_locked(lock));
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#endif
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__asm__ __volatile__(
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spin_unlock_string
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);
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}
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#else
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#define spin_unlock_string \
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"xchgb %b0, %1" \
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:"=q" (oldval), "=m" (lock->slock) \
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:"0" (oldval) : "memory"
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static inline void _raw_spin_unlock(spinlock_t *lock)
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{
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char oldval = 1;
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#ifdef CONFIG_DEBUG_SPINLOCK
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BUG_ON(lock->magic != SPINLOCK_MAGIC);
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BUG_ON(!spin_is_locked(lock));
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#endif
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__asm__ __volatile__(
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spin_unlock_string
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);
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}
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#endif
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static inline int _raw_spin_trylock(spinlock_t *lock)
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{
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char oldval;
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__asm__ __volatile__(
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"xchgb %b0,%1"
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:"=q" (oldval), "=m" (lock->slock)
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:"0" (0) : "memory");
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return oldval > 0;
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}
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static inline void _raw_spin_lock(spinlock_t *lock)
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{
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#ifdef CONFIG_DEBUG_SPINLOCK
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if (unlikely(lock->magic != SPINLOCK_MAGIC)) {
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printk("eip: %p\n", __builtin_return_address(0));
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BUG();
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}
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#endif
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__asm__ __volatile__(
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spin_lock_string
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:"=m" (lock->slock) : : "memory");
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}
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static inline void _raw_spin_lock_flags (spinlock_t *lock, unsigned long flags)
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{
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#ifdef CONFIG_DEBUG_SPINLOCK
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if (unlikely(lock->magic != SPINLOCK_MAGIC)) {
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printk("eip: %p\n", __builtin_return_address(0));
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BUG();
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}
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#endif
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__asm__ __volatile__(
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spin_lock_string_flags
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:"=m" (lock->slock) : "r" (flags) : "memory");
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}
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/*
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* Read-write spinlocks, allowing multiple readers
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* but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts
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* but no interrupt writers. For those circumstances we
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* can "mix" irq-safe locks - any writer needs to get a
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* irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*/
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typedef struct {
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volatile unsigned int lock;
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#ifdef CONFIG_DEBUG_SPINLOCK
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unsigned magic;
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#endif
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#ifdef CONFIG_PREEMPT
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unsigned int break_lock;
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#endif
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} rwlock_t;
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#define RWLOCK_MAGIC 0xdeaf1eed
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#ifdef CONFIG_DEBUG_SPINLOCK
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#define RWLOCK_MAGIC_INIT , RWLOCK_MAGIC
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#else
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#define RWLOCK_MAGIC_INIT /* */
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#endif
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#define RW_LOCK_UNLOCKED (rwlock_t) { RW_LOCK_BIAS RWLOCK_MAGIC_INIT }
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#define rwlock_init(x) do { *(x) = RW_LOCK_UNLOCKED; } while(0)
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/**
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* read_can_lock - would read_trylock() succeed?
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* @lock: the rwlock in question.
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*/
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#define read_can_lock(x) ((int)(x)->lock > 0)
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/**
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* write_can_lock - would write_trylock() succeed?
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* @lock: the rwlock in question.
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*/
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#define write_can_lock(x) ((x)->lock == RW_LOCK_BIAS)
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/*
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* On x86, we implement read-write locks as a 32-bit counter
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* with the high bit (sign) being the "contended" bit.
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*
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* The inline assembly is non-obvious. Think about it.
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*
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* Changed to use the same technique as rw semaphores. See
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* semaphore.h for details. -ben
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*/
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/* the spinlock helpers are in arch/i386/kernel/semaphore.c */
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static inline void _raw_read_lock(rwlock_t *rw)
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{
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#ifdef CONFIG_DEBUG_SPINLOCK
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BUG_ON(rw->magic != RWLOCK_MAGIC);
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#endif
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__build_read_lock(rw, "__read_lock_failed");
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}
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static inline void _raw_write_lock(rwlock_t *rw)
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{
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#ifdef CONFIG_DEBUG_SPINLOCK
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BUG_ON(rw->magic != RWLOCK_MAGIC);
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#endif
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__build_write_lock(rw, "__write_lock_failed");
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}
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#define _raw_read_unlock(rw) asm volatile("lock ; incl %0" :"=m" ((rw)->lock) : : "memory")
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#define _raw_write_unlock(rw) asm volatile("lock ; addl $" RW_LOCK_BIAS_STR ",%0":"=m" ((rw)->lock) : : "memory")
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static inline int _raw_read_trylock(rwlock_t *lock)
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{
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atomic_t *count = (atomic_t *)lock;
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atomic_dec(count);
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if (atomic_read(count) >= 0)
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return 1;
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atomic_inc(count);
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return 0;
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}
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static inline int _raw_write_trylock(rwlock_t *lock)
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{
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atomic_t *count = (atomic_t *)lock;
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if (atomic_sub_and_test(RW_LOCK_BIAS, count))
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return 1;
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atomic_add(RW_LOCK_BIAS, count);
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return 0;
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}
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#endif /* __ASM_SPINLOCK_H */
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