188 lines
3.9 KiB
ArmAsm
188 lines
3.9 KiB
ArmAsm
/*
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* Copyright 2011 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*
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* This routine is a helper for migrating the home of a set of pages to
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* a new cpu. See the documentation in homecache.c for more information.
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*/
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#include <linux/linkage.h>
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#include <linux/threads.h>
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#include <asm/page.h>
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#include <asm/thread_info.h>
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#include <asm/types.h>
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#include <asm/asm-offsets.h>
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#include <hv/hypervisor.h>
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.text
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/*
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* First, some definitions that apply to all the code in the file.
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*/
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/* Locals (caller-save) */
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#define r_tmp r10
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#define r_save_sp r11
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/* What we save where in the stack frame; must include all callee-saves. */
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#define FRAME_SP 8
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#define FRAME_R30 16
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#define FRAME_R31 24
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#define FRAME_R32 32
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#define FRAME_R33 40
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#define FRAME_SIZE 48
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/*
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* On entry:
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*
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* r0 the new context PA to install (moved to r_context)
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* r1 PTE to use for context access (moved to r_access)
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* r2 ASID to use for new context (moved to r_asid)
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* r3 pointer to cpumask with just this cpu set in it (r_my_cpumask)
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*/
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/* Arguments (caller-save) */
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#define r_context_in r0
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#define r_access_in r1
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#define r_asid_in r2
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#define r_my_cpumask r3
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/* Locals (callee-save); must not be more than FRAME_xxx above. */
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#define r_save_ics r30
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#define r_context r31
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#define r_access r32
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#define r_asid r33
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/*
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* Caller-save locals and frame constants are the same as
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* for homecache_migrate_stack_and_flush.
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*/
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STD_ENTRY(flush_and_install_context)
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/*
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* Create a stack frame; we can't touch it once we flush the
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* cache until we install the new page table and flush the TLB.
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*/
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{
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move r_save_sp, sp
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st sp, lr
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addi sp, sp, -FRAME_SIZE
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}
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addi r_tmp, sp, FRAME_SP
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{
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st r_tmp, r_save_sp
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addi r_tmp, sp, FRAME_R30
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}
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{
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st r_tmp, r30
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addi r_tmp, sp, FRAME_R31
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}
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{
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st r_tmp, r31
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addi r_tmp, sp, FRAME_R32
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}
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{
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st r_tmp, r32
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addi r_tmp, sp, FRAME_R33
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}
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st r_tmp, r33
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/* Move some arguments to callee-save registers. */
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{
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move r_context, r_context_in
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move r_access, r_access_in
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}
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move r_asid, r_asid_in
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/* Disable interrupts, since we can't use our stack. */
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{
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mfspr r_save_ics, INTERRUPT_CRITICAL_SECTION
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movei r_tmp, 1
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}
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mtspr INTERRUPT_CRITICAL_SECTION, r_tmp
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/* First, flush our L2 cache. */
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{
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move r0, zero /* cache_pa */
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moveli r1, hw2_last(HV_FLUSH_EVICT_L2) /* cache_control */
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}
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{
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shl16insli r1, r1, hw1(HV_FLUSH_EVICT_L2)
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move r2, r_my_cpumask /* cache_cpumask */
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}
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{
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shl16insli r1, r1, hw0(HV_FLUSH_EVICT_L2)
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move r3, zero /* tlb_va */
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}
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{
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move r4, zero /* tlb_length */
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move r5, zero /* tlb_pgsize */
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}
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{
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move r6, zero /* tlb_cpumask */
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move r7, zero /* asids */
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}
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{
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move r8, zero /* asidcount */
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jal hv_flush_remote
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}
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bnez r0, 1f
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/* Now install the new page table. */
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{
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move r0, r_context
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move r1, r_access
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}
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{
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move r2, r_asid
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movei r3, HV_CTX_DIRECTIO
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}
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jal hv_install_context
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bnez r0, 1f
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/* Finally, flush the TLB. */
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{
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movei r0, 0 /* preserve_global */
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jal hv_flush_all
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}
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1: /* Reset interrupts back how they were before. */
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mtspr INTERRUPT_CRITICAL_SECTION, r_save_ics
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/* Restore the callee-saved registers and return. */
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addli lr, sp, FRAME_SIZE
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{
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ld lr, lr
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addli r_tmp, sp, FRAME_R30
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}
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{
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ld r30, r_tmp
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addli r_tmp, sp, FRAME_R31
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}
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{
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ld r31, r_tmp
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addli r_tmp, sp, FRAME_R32
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}
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{
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ld r32, r_tmp
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addli r_tmp, sp, FRAME_R33
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}
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{
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ld r33, r_tmp
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addi sp, sp, FRAME_SIZE
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}
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jrp lr
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STD_ENDPROC(flush_and_install_context)
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