288 lines
7.1 KiB
C
288 lines
7.1 KiB
C
/*
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* File: arch/blackfin/kernel/cplb-nompu-c/cplbmgr.c
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* Based on: arch/blackfin/kernel/cplb-mpu/cplbmgr.c
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* Author: Michael McTernan <mmcternan@airvana.com>
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*
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* Created: 01Nov2008
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* Description: CPLB miss handler.
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*
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* Modified:
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* Copyright 2008 Airvana Inc.
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* Copyright 2004-2007 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <asm/blackfin.h>
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#include <asm/cplbinit.h>
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#include <asm/cplb.h>
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#include <asm/mmu_context.h>
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/*
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* WARNING
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*
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* This file is compiled with certain -ffixed-reg options. We have to
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* make sure not to call any functions here that could clobber these
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* registers.
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*/
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int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
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int nr_dcplb_supv_miss[NR_CPUS], nr_icplb_supv_miss[NR_CPUS];
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int nr_cplb_flush[NR_CPUS], nr_dcplb_prot[NR_CPUS];
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#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
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#define MGR_ATTR __attribute__((l1_text))
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#else
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#define MGR_ATTR
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#endif
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/*
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* We're in an exception handler. The normal cli nop nop workaround
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* isn't going to do very much, as the only thing that can interrupt
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* us is an NMI, and the cli isn't going to stop that.
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*/
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#define NOWA_SSYNC __asm__ __volatile__ ("ssync;")
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/* Anomaly handlers provide SSYNCs, so avoid extra if anomaly is present */
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#if ANOMALY_05000125
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#define bfin_write_DMEM_CONTROL_SSYNC(v) bfin_write_DMEM_CONTROL(v)
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#define bfin_write_IMEM_CONTROL_SSYNC(v) bfin_write_IMEM_CONTROL(v)
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#else
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#define bfin_write_DMEM_CONTROL_SSYNC(v) \
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do { NOWA_SSYNC; bfin_write_DMEM_CONTROL(v); NOWA_SSYNC; } while (0)
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#define bfin_write_IMEM_CONTROL_SSYNC(v) \
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do { NOWA_SSYNC; bfin_write_IMEM_CONTROL(v); NOWA_SSYNC; } while (0)
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#endif
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static inline void write_dcplb_data(int cpu, int idx, unsigned long data,
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unsigned long addr)
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{
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unsigned long ctrl = bfin_read_DMEM_CONTROL();
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bfin_write_DMEM_CONTROL_SSYNC(ctrl & ~ENDCPLB);
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bfin_write32(DCPLB_DATA0 + idx * 4, data);
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bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
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bfin_write_DMEM_CONTROL_SSYNC(ctrl);
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#ifdef CONFIG_CPLB_INFO
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dcplb_tbl[cpu][idx].addr = addr;
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dcplb_tbl[cpu][idx].data = data;
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#endif
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}
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static inline void write_icplb_data(int cpu, int idx, unsigned long data,
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unsigned long addr)
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{
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unsigned long ctrl = bfin_read_IMEM_CONTROL();
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bfin_write_IMEM_CONTROL_SSYNC(ctrl & ~ENICPLB);
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bfin_write32(ICPLB_DATA0 + idx * 4, data);
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bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
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bfin_write_IMEM_CONTROL_SSYNC(ctrl);
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#ifdef CONFIG_CPLB_INFO
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icplb_tbl[cpu][idx].addr = addr;
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icplb_tbl[cpu][idx].data = data;
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#endif
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}
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/*
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* Given the contents of the status register, return the index of the
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* CPLB that caused the fault.
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*/
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static inline int faulting_cplb_index(int status)
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{
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int signbits = __builtin_bfin_norm_fr1x32(status & 0xFFFF);
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return 30 - signbits;
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}
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/*
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* Given the contents of the status register and the DCPLB_DATA contents,
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* return true if a write access should be permitted.
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*/
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static inline int write_permitted(int status, unsigned long data)
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{
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if (status & FAULT_USERSUPV)
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return !!(data & CPLB_SUPV_WR);
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else
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return !!(data & CPLB_USER_WR);
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}
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/* Counters to implement round-robin replacement. */
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static int icplb_rr_index[NR_CPUS] PDT_ATTR;
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static int dcplb_rr_index[NR_CPUS] PDT_ATTR;
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/*
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* Find an ICPLB entry to be evicted and return its index.
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*/
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static int evict_one_icplb(int cpu)
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{
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int i = first_switched_icplb + icplb_rr_index[cpu];
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if (i >= MAX_CPLBS) {
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i -= MAX_CPLBS - first_switched_icplb;
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icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb;
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}
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icplb_rr_index[cpu]++;
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return i;
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}
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static int evict_one_dcplb(int cpu)
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{
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int i = first_switched_dcplb + dcplb_rr_index[cpu];
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if (i >= MAX_CPLBS) {
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i -= MAX_CPLBS - first_switched_dcplb;
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dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb;
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}
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dcplb_rr_index[cpu]++;
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return i;
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}
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MGR_ATTR static int icplb_miss(int cpu)
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{
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unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
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int status = bfin_read_ICPLB_STATUS();
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int idx;
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unsigned long i_data, base, addr1, eaddr;
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nr_icplb_miss[cpu]++;
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if (unlikely(status & FAULT_USERSUPV))
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nr_icplb_supv_miss[cpu]++;
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base = 0;
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idx = 0;
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do {
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eaddr = icplb_bounds[idx].eaddr;
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if (addr < eaddr)
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break;
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base = eaddr;
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} while (++idx < icplb_nr_bounds);
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if (unlikely(idx == icplb_nr_bounds))
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return CPLB_NO_ADDR_MATCH;
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i_data = icplb_bounds[idx].data;
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if (unlikely(i_data == 0))
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return CPLB_NO_ADDR_MATCH;
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addr1 = addr & ~(SIZE_4M - 1);
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addr &= ~(SIZE_1M - 1);
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i_data |= PAGE_SIZE_1MB;
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if (addr1 >= base && (addr1 + SIZE_4M) <= eaddr) {
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/*
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* This works because
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* (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB.
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*/
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i_data |= PAGE_SIZE_4MB;
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addr = addr1;
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}
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/* Pick entry to evict */
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idx = evict_one_icplb(cpu);
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write_icplb_data(cpu, idx, i_data, addr);
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return CPLB_RELOADED;
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}
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MGR_ATTR static int dcplb_miss(int cpu)
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{
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unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
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int status = bfin_read_DCPLB_STATUS();
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int idx;
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unsigned long d_data, base, addr1, eaddr;
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nr_dcplb_miss[cpu]++;
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if (unlikely(status & FAULT_USERSUPV))
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nr_dcplb_supv_miss[cpu]++;
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base = 0;
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idx = 0;
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do {
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eaddr = dcplb_bounds[idx].eaddr;
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if (addr < eaddr)
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break;
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base = eaddr;
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} while (++idx < dcplb_nr_bounds);
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if (unlikely(idx == dcplb_nr_bounds))
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return CPLB_NO_ADDR_MATCH;
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d_data = dcplb_bounds[idx].data;
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if (unlikely(d_data == 0))
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return CPLB_NO_ADDR_MATCH;
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addr1 = addr & ~(SIZE_4M - 1);
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addr &= ~(SIZE_1M - 1);
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d_data |= PAGE_SIZE_1MB;
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if (addr1 >= base && (addr1 + SIZE_4M) <= eaddr) {
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/*
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* This works because
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* (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB.
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*/
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d_data |= PAGE_SIZE_4MB;
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addr = addr1;
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}
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/* Pick entry to evict */
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idx = evict_one_dcplb(cpu);
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write_dcplb_data(cpu, idx, d_data, addr);
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return CPLB_RELOADED;
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}
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MGR_ATTR static noinline int dcplb_protection_fault(int cpu)
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{
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int status = bfin_read_DCPLB_STATUS();
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nr_dcplb_prot[cpu]++;
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if (likely(status & FAULT_RW)) {
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int idx = faulting_cplb_index(status);
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unsigned long regaddr = DCPLB_DATA0 + idx * 4;
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unsigned long data = bfin_read32(regaddr);
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/* Check if fault is to dirty a clean page */
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if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) &&
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write_permitted(status, data)) {
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dcplb_tbl[cpu][idx].data = data;
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bfin_write32(regaddr, data);
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return CPLB_RELOADED;
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}
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}
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return CPLB_PROT_VIOL;
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}
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MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs)
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{
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int cause = seqstat & 0x3f;
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unsigned int cpu = smp_processor_id();
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switch (cause) {
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case 0x2C:
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return icplb_miss(cpu);
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case 0x26:
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return dcplb_miss(cpu);
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default:
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if (unlikely(cause == 0x23))
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return dcplb_protection_fault(cpu);
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return CPLB_UNKNOWN_ERR;
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}
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}
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