475 lines
10 KiB
C
475 lines
10 KiB
C
/* linux/arch/arm/plat-s3c24xx/pwm-clock.c
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*
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* Copyright (c) 2007 Simtec Electronics
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* Copyright (c) 2007, 2008 Ben Dooks
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* Ben Dooks <ben-linux@fluff.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/log2.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <asm/irq.h>
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#include <plat/clock.h>
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#include <plat/cpu.h>
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#include <plat/regs-timer.h>
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#include <plat/pwm-clock.h>
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/* Each of the timers 0 through 5 go through the following
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* clock tree, with the inputs depending on the timers.
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*
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* pclk ---- [ prescaler 0 ] -+---> timer 0
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* +---> timer 1
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*
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* pclk ---- [ prescaler 1 ] -+---> timer 2
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* +---> timer 3
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* \---> timer 4
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*
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* Which are fed into the timers as so:
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*
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* prescaled 0 ---- [ div 2,4,8,16 ] ---\
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* [mux] -> timer 0
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* tclk 0 ------------------------------/
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*
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* prescaled 0 ---- [ div 2,4,8,16 ] ---\
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* [mux] -> timer 1
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* tclk 0 ------------------------------/
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*
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*
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* prescaled 1 ---- [ div 2,4,8,16 ] ---\
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* [mux] -> timer 2
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* tclk 1 ------------------------------/
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*
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* prescaled 1 ---- [ div 2,4,8,16 ] ---\
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* [mux] -> timer 3
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* tclk 1 ------------------------------/
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*
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* prescaled 1 ---- [ div 2,4,8, 16 ] --\
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* [mux] -> timer 4
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* tclk 1 ------------------------------/
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*
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* Since the mux and the divider are tied together in the
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* same register space, it is impossible to set the parent
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* and the rate at the same time. To avoid this, we add an
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* intermediate 'prescaled-and-divided' clock to select
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* as the parent for the timer input clock called tdiv.
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*
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* prescaled clk --> pwm-tdiv ---\
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* [ mux ] --> timer X
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* tclk -------------------------/
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*/
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static struct clk clk_timer_scaler[];
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static unsigned long clk_pwm_scaler_get_rate(struct clk *clk)
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{
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unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0);
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if (clk == &clk_timer_scaler[1]) {
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tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK;
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tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT;
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} else {
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tcfg0 &= S3C2410_TCFG_PRESCALER0_MASK;
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}
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return clk_get_rate(clk->parent) / (tcfg0 + 1);
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}
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static unsigned long clk_pwm_scaler_round_rate(struct clk *clk,
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unsigned long rate)
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{
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unsigned long parent_rate = clk_get_rate(clk->parent);
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unsigned long divisor = parent_rate / rate;
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if (divisor > 256)
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divisor = 256;
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else if (divisor < 2)
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divisor = 2;
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return parent_rate / divisor;
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}
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static int clk_pwm_scaler_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long round = clk_pwm_scaler_round_rate(clk, rate);
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unsigned long tcfg0;
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unsigned long divisor;
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unsigned long flags;
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divisor = clk_get_rate(clk->parent) / round;
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divisor--;
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local_irq_save(flags);
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tcfg0 = __raw_readl(S3C2410_TCFG0);
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if (clk == &clk_timer_scaler[1]) {
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tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
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tcfg0 |= divisor << S3C2410_TCFG_PRESCALER1_SHIFT;
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} else {
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tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK;
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tcfg0 |= divisor;
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}
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__raw_writel(tcfg0, S3C2410_TCFG0);
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local_irq_restore(flags);
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return 0;
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}
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static struct clk_ops clk_pwm_scaler_ops = {
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.get_rate = clk_pwm_scaler_get_rate,
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.set_rate = clk_pwm_scaler_set_rate,
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.round_rate = clk_pwm_scaler_round_rate,
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};
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static struct clk clk_timer_scaler[] = {
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[0] = {
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.name = "pwm-scaler0",
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.id = -1,
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.ops = &clk_pwm_scaler_ops,
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},
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[1] = {
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.name = "pwm-scaler1",
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.id = -1,
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.ops = &clk_pwm_scaler_ops,
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},
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};
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static struct clk clk_timer_tclk[] = {
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[0] = {
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.name = "pwm-tclk0",
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.id = -1,
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},
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[1] = {
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.name = "pwm-tclk1",
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.id = -1,
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},
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};
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struct pwm_tdiv_clk {
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struct clk clk;
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unsigned int divisor;
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};
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static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk)
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{
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return container_of(clk, struct pwm_tdiv_clk, clk);
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}
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static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)
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{
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unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
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unsigned int divisor;
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tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
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tcfg1 &= S3C2410_TCFG1_MUX_MASK;
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if (pwm_cfg_src_is_tclk(tcfg1))
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divisor = to_tdiv(clk)->divisor;
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else
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divisor = tcfg_to_divisor(tcfg1);
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return clk_get_rate(clk->parent) / divisor;
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}
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static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk,
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unsigned long rate)
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{
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unsigned long parent_rate;
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unsigned long divisor;
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parent_rate = clk_get_rate(clk->parent);
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divisor = parent_rate / rate;
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if (divisor <= 1 && pwm_tdiv_has_div1())
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divisor = 1;
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else if (divisor <= 2)
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divisor = 2;
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else if (divisor <= 4)
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divisor = 4;
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else if (divisor <= 8)
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divisor = 8;
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else
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divisor = 16;
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return parent_rate / divisor;
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}
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static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk)
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{
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return pwm_tdiv_div_bits(divclk->divisor);
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}
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static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk)
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{
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unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
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unsigned long bits = clk_pwm_tdiv_bits(divclk);
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unsigned long flags;
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unsigned long shift = S3C2410_TCFG1_SHIFT(divclk->clk.id);
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local_irq_save(flags);
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tcfg1 = __raw_readl(S3C2410_TCFG1);
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tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
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tcfg1 |= bits << shift;
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__raw_writel(tcfg1, S3C2410_TCFG1);
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local_irq_restore(flags);
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}
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static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate)
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{
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struct pwm_tdiv_clk *divclk = to_tdiv(clk);
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unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
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unsigned long parent_rate = clk_get_rate(clk->parent);
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unsigned long divisor;
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tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
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tcfg1 &= S3C2410_TCFG1_MUX_MASK;
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rate = clk_round_rate(clk, rate);
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divisor = parent_rate / rate;
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if (divisor > 16)
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return -EINVAL;
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divclk->divisor = divisor;
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/* Update the current MUX settings if we are currently
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* selected as the clock source for this clock. */
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if (!pwm_cfg_src_is_tclk(tcfg1))
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clk_pwm_tdiv_update(divclk);
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return 0;
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}
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static struct clk_ops clk_tdiv_ops = {
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.get_rate = clk_pwm_tdiv_get_rate,
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.set_rate = clk_pwm_tdiv_set_rate,
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.round_rate = clk_pwm_tdiv_round_rate,
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};
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static struct pwm_tdiv_clk clk_timer_tdiv[] = {
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[0] = {
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.clk = {
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.name = "pwm-tdiv",
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.devname = "s3c24xx-pwm.0",
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.ops = &clk_tdiv_ops,
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.parent = &clk_timer_scaler[0],
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},
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},
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[1] = {
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.clk = {
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.name = "pwm-tdiv",
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.devname = "s3c24xx-pwm.1",
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.ops = &clk_tdiv_ops,
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.parent = &clk_timer_scaler[0],
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}
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},
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[2] = {
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.clk = {
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.name = "pwm-tdiv",
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.devname = "s3c24xx-pwm.2",
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.ops = &clk_tdiv_ops,
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.parent = &clk_timer_scaler[1],
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},
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},
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[3] = {
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.clk = {
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.name = "pwm-tdiv",
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.devname = "s3c24xx-pwm.3",
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.ops = &clk_tdiv_ops,
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.parent = &clk_timer_scaler[1],
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},
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},
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[4] = {
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.clk = {
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.name = "pwm-tdiv",
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.devname = "s3c24xx-pwm.4",
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.ops = &clk_tdiv_ops,
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.parent = &clk_timer_scaler[1],
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},
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},
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};
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static int __init clk_pwm_tdiv_register(unsigned int id)
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{
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struct pwm_tdiv_clk *divclk = &clk_timer_tdiv[id];
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unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
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tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
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tcfg1 &= S3C2410_TCFG1_MUX_MASK;
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divclk->clk.id = id;
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divclk->divisor = tcfg_to_divisor(tcfg1);
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return s3c24xx_register_clock(&divclk->clk);
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}
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static inline struct clk *s3c24xx_pwmclk_tclk(unsigned int id)
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{
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return (id >= 2) ? &clk_timer_tclk[1] : &clk_timer_tclk[0];
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}
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static inline struct clk *s3c24xx_pwmclk_tdiv(unsigned int id)
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{
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return &clk_timer_tdiv[id].clk;
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}
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static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
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{
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unsigned int id = clk->id;
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unsigned long tcfg1;
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unsigned long flags;
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unsigned long bits;
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unsigned long shift = S3C2410_TCFG1_SHIFT(id);
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unsigned long mux_tclk;
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if (soc_is_s3c24xx())
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mux_tclk = S3C2410_TCFG1_MUX_TCLK;
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else if (soc_is_s5p6440() || soc_is_s5p6450())
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mux_tclk = 0;
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else
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mux_tclk = S3C64XX_TCFG1_MUX_TCLK;
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if (parent == s3c24xx_pwmclk_tclk(id))
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bits = mux_tclk << shift;
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else if (parent == s3c24xx_pwmclk_tdiv(id))
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bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift;
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else
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return -EINVAL;
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clk->parent = parent;
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local_irq_save(flags);
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tcfg1 = __raw_readl(S3C2410_TCFG1);
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tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
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__raw_writel(tcfg1 | bits, S3C2410_TCFG1);
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local_irq_restore(flags);
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return 0;
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}
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static struct clk_ops clk_tin_ops = {
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.set_parent = clk_pwm_tin_set_parent,
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};
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static struct clk clk_tin[] = {
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[0] = {
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.name = "pwm-tin",
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.devname = "s3c24xx-pwm.0",
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.id = 0,
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.ops = &clk_tin_ops,
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},
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[1] = {
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.name = "pwm-tin",
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.devname = "s3c24xx-pwm.1",
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.id = 1,
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.ops = &clk_tin_ops,
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},
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[2] = {
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.name = "pwm-tin",
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.devname = "s3c24xx-pwm.2",
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.id = 2,
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.ops = &clk_tin_ops,
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},
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[3] = {
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.name = "pwm-tin",
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.devname = "s3c24xx-pwm.3",
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.id = 3,
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.ops = &clk_tin_ops,
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},
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[4] = {
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.name = "pwm-tin",
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.devname = "s3c24xx-pwm.4",
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.id = 4,
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.ops = &clk_tin_ops,
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},
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};
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static __init int clk_pwm_tin_register(struct clk *pwm)
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{
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unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
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unsigned int id = pwm->id;
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struct clk *parent;
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int ret;
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ret = s3c24xx_register_clock(pwm);
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if (ret < 0)
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return ret;
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tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
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tcfg1 &= S3C2410_TCFG1_MUX_MASK;
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if (pwm_cfg_src_is_tclk(tcfg1))
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parent = s3c24xx_pwmclk_tclk(id);
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else
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parent = s3c24xx_pwmclk_tdiv(id);
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return clk_set_parent(pwm, parent);
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}
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/**
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* s3c_pwmclk_init() - initialise pwm clocks
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*
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* Initialise and register the clocks which provide the inputs for the
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* pwm timer blocks.
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*
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* Note, this call is required by the time core, so must be called after
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* the base clocks are added and before any of the initcalls are run.
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*/
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__init void s3c_pwmclk_init(void)
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{
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struct clk *clk_timers;
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unsigned int clk;
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int ret;
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clk_timers = clk_get(NULL, "timers");
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if (IS_ERR(clk_timers)) {
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printk(KERN_ERR "%s: no parent clock\n", __func__);
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return;
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}
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for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++)
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clk_timer_scaler[clk].parent = clk_timers;
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s3c_register_clocks(clk_timer_scaler, ARRAY_SIZE(clk_timer_scaler));
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s3c_register_clocks(clk_timer_tclk, ARRAY_SIZE(clk_timer_tclk));
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for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) {
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ret = clk_pwm_tdiv_register(clk);
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if (ret < 0) {
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printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk);
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return;
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}
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}
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for (clk = 0; clk < ARRAY_SIZE(clk_tin); clk++) {
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ret = clk_pwm_tin_register(&clk_tin[clk]);
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if (ret < 0) {
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printk(KERN_ERR "error adding pwm%d tin clock\n", clk);
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return;
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}
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}
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}
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