331 lines
7.8 KiB
C
331 lines
7.8 KiB
C
/***************************************************************************/
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/*
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* linux/arch/m68knommu/platform/5249/config.c
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*
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* Copyright (C) 2002, Greg Ungerer (gerg@snapgear.com)
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*/
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/***************************************************************************/
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/spi/spi.h>
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#include <linux/gpio.h>
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#include <asm/machdep.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/mcfuart.h>
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#include <asm/mcfqspi.h>
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/***************************************************************************/
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static struct mcf_platform_uart m5249_uart_platform[] = {
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{
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.mapbase = MCF_MBAR + MCFUART_BASE1,
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.irq = 73,
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},
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{
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.mapbase = MCF_MBAR + MCFUART_BASE2,
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.irq = 74,
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},
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{ },
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};
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static struct platform_device m5249_uart = {
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.name = "mcfuart",
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.id = 0,
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.dev.platform_data = m5249_uart_platform,
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};
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#ifdef CONFIG_M5249C3
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static struct resource m5249_smc91x_resources[] = {
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{
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.start = 0xe0000300,
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.end = 0xe0000300 + 0x100,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MCFINTC2_GPIOIRQ6,
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.end = MCFINTC2_GPIOIRQ6,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device m5249_smc91x = {
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.name = "smc91x",
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.id = 0,
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.num_resources = ARRAY_SIZE(m5249_smc91x_resources),
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.resource = m5249_smc91x_resources,
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};
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#endif /* CONFIG_M5249C3 */
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#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
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static struct resource m5249_qspi_resources[] = {
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{
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.start = MCFQSPI_IOBASE,
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.end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MCF_IRQ_QSPI,
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.end = MCF_IRQ_QSPI,
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.flags = IORESOURCE_IRQ,
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},
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};
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#define MCFQSPI_CS0 29
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#define MCFQSPI_CS1 24
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#define MCFQSPI_CS2 21
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#define MCFQSPI_CS3 22
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static int m5249_cs_setup(struct mcfqspi_cs_control *cs_control)
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{
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int status;
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status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
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if (status) {
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pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
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goto fail0;
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}
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status = gpio_direction_output(MCFQSPI_CS0, 1);
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if (status) {
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pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
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goto fail1;
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}
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status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
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if (status) {
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pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
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goto fail1;
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}
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status = gpio_direction_output(MCFQSPI_CS1, 1);
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if (status) {
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pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
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goto fail2;
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}
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status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
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if (status) {
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pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
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goto fail2;
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}
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status = gpio_direction_output(MCFQSPI_CS2, 1);
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if (status) {
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pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
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goto fail3;
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}
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status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
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if (status) {
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pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
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goto fail3;
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}
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status = gpio_direction_output(MCFQSPI_CS3, 1);
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if (status) {
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pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
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goto fail4;
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}
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return 0;
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fail4:
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gpio_free(MCFQSPI_CS3);
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fail3:
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gpio_free(MCFQSPI_CS2);
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fail2:
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gpio_free(MCFQSPI_CS1);
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fail1:
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gpio_free(MCFQSPI_CS0);
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fail0:
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return status;
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}
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static void m5249_cs_teardown(struct mcfqspi_cs_control *cs_control)
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{
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gpio_free(MCFQSPI_CS3);
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gpio_free(MCFQSPI_CS2);
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gpio_free(MCFQSPI_CS1);
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gpio_free(MCFQSPI_CS0);
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}
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static void m5249_cs_select(struct mcfqspi_cs_control *cs_control,
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u8 chip_select, bool cs_high)
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{
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switch (chip_select) {
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case 0:
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gpio_set_value(MCFQSPI_CS0, cs_high);
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break;
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case 1:
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gpio_set_value(MCFQSPI_CS1, cs_high);
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break;
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case 2:
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gpio_set_value(MCFQSPI_CS2, cs_high);
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break;
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case 3:
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gpio_set_value(MCFQSPI_CS3, cs_high);
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break;
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}
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}
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static void m5249_cs_deselect(struct mcfqspi_cs_control *cs_control,
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u8 chip_select, bool cs_high)
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{
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switch (chip_select) {
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case 0:
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gpio_set_value(MCFQSPI_CS0, !cs_high);
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break;
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case 1:
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gpio_set_value(MCFQSPI_CS1, !cs_high);
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break;
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case 2:
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gpio_set_value(MCFQSPI_CS2, !cs_high);
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break;
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case 3:
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gpio_set_value(MCFQSPI_CS3, !cs_high);
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break;
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}
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}
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static struct mcfqspi_cs_control m5249_cs_control = {
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.setup = m5249_cs_setup,
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.teardown = m5249_cs_teardown,
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.select = m5249_cs_select,
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.deselect = m5249_cs_deselect,
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};
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static struct mcfqspi_platform_data m5249_qspi_data = {
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.bus_num = 0,
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.num_chipselect = 4,
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.cs_control = &m5249_cs_control,
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};
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static struct platform_device m5249_qspi = {
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.name = "mcfqspi",
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.id = 0,
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.num_resources = ARRAY_SIZE(m5249_qspi_resources),
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.resource = m5249_qspi_resources,
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.dev.platform_data = &m5249_qspi_data,
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};
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static void __init m5249_qspi_init(void)
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{
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/* QSPI irq setup */
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writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
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MCF_MBAR + MCFSIM_QSPIICR);
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mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
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}
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#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
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static struct platform_device *m5249_devices[] __initdata = {
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&m5249_uart,
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#ifdef CONFIG_M5249C3
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&m5249_smc91x,
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#endif
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#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
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&m5249_qspi,
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#endif
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};
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/***************************************************************************/
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static void __init m5249_uart_init_line(int line, int irq)
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{
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if (line == 0) {
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writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
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writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
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mcf_mapirq2imr(irq, MCFINTC_UART0);
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} else if (line == 1) {
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writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
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writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
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mcf_mapirq2imr(irq, MCFINTC_UART1);
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}
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}
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static void __init m5249_uarts_init(void)
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{
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const int nrlines = ARRAY_SIZE(m5249_uart_platform);
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int line;
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for (line = 0; (line < nrlines); line++)
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m5249_uart_init_line(line, m5249_uart_platform[line].irq);
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}
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/***************************************************************************/
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#ifdef CONFIG_M5249C3
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static void __init m5249_smc91x_init(void)
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{
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u32 gpio;
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/* Set the GPIO line as interrupt source for smc91x device */
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gpio = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
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writel(gpio | 0x40, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
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gpio = readl(MCF_MBAR2 + MCFSIM2_INTLEVEL5);
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writel(gpio | 0x04000000, MCF_MBAR2 + MCFSIM2_INTLEVEL5);
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}
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#endif /* CONFIG_M5249C3 */
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/***************************************************************************/
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static void __init m5249_timers_init(void)
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{
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/* Timer1 is always used as system timer */
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writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
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MCF_MBAR + MCFSIM_TIMER1ICR);
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mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
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#ifdef CONFIG_HIGHPROFILE
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/* Timer2 is to be used as a high speed profile timer */
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writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
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MCF_MBAR + MCFSIM_TIMER2ICR);
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mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
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#endif
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}
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/***************************************************************************/
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void m5249_cpu_reset(void)
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{
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local_irq_disable();
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/* Set watchdog to soft reset, and enabled */
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__raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
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for (;;)
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/* wait for watchdog to timeout */;
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}
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/***************************************************************************/
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void __init config_BSP(char *commandp, int size)
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{
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mach_reset = m5249_cpu_reset;
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m5249_timers_init();
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m5249_uarts_init();
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#ifdef CONFIG_M5249C3
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m5249_smc91x_init();
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#endif
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#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
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m5249_qspi_init();
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#endif
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}
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/***************************************************************************/
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static int __init init_BSP(void)
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{
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platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices));
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return 0;
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}
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arch_initcall(init_BSP);
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/***************************************************************************/
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