258 lines
6.2 KiB
C
258 lines
6.2 KiB
C
/*
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* Author: Andy Fleming <afleming@freescale.com>
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* Kumar Gala <galak@kernel.crashing.org>
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*
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* Copyright 2006-2008, 2011 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/kexec.h>
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#include <linux/highmem.h>
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#include <asm/machdep.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/mpic.h>
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#include <asm/cacheflush.h>
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#include <asm/dbell.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/mpic.h>
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extern void __early_start(void);
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#define BOOT_ENTRY_ADDR_UPPER 0
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#define BOOT_ENTRY_ADDR_LOWER 1
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#define BOOT_ENTRY_R3_UPPER 2
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#define BOOT_ENTRY_R3_LOWER 3
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#define BOOT_ENTRY_RESV 4
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#define BOOT_ENTRY_PIR 5
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#define BOOT_ENTRY_R6_UPPER 6
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#define BOOT_ENTRY_R6_LOWER 7
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#define NUM_BOOT_ENTRY 8
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#define SIZE_BOOT_ENTRY (NUM_BOOT_ENTRY * sizeof(u32))
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static int __init
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smp_85xx_kick_cpu(int nr)
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{
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unsigned long flags;
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const u64 *cpu_rel_addr;
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__iomem u32 *bptr_vaddr;
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struct device_node *np;
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int n = 0, hw_cpu = get_hard_smp_processor_id(nr);
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int ioremappable;
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WARN_ON(nr < 0 || nr >= NR_CPUS);
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WARN_ON(hw_cpu < 0 || hw_cpu >= NR_CPUS);
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pr_debug("smp_85xx_kick_cpu: kick CPU #%d\n", nr);
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np = of_get_cpu_node(nr, NULL);
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cpu_rel_addr = of_get_property(np, "cpu-release-addr", NULL);
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if (cpu_rel_addr == NULL) {
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printk(KERN_ERR "No cpu-release-addr for cpu %d\n", nr);
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return -ENOENT;
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}
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/*
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* A secondary core could be in a spinloop in the bootpage
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* (0xfffff000), somewhere in highmem, or somewhere in lowmem.
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* The bootpage and highmem can be accessed via ioremap(), but
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* we need to directly access the spinloop if its in lowmem.
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*/
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ioremappable = *cpu_rel_addr > virt_to_phys(high_memory);
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/* Map the spin table */
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if (ioremappable)
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bptr_vaddr = ioremap(*cpu_rel_addr, SIZE_BOOT_ENTRY);
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else
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bptr_vaddr = phys_to_virt(*cpu_rel_addr);
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local_irq_save(flags);
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out_be32(bptr_vaddr + BOOT_ENTRY_PIR, hw_cpu);
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#ifdef CONFIG_PPC32
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out_be32(bptr_vaddr + BOOT_ENTRY_ADDR_LOWER, __pa(__early_start));
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if (!ioremappable)
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flush_dcache_range((ulong)bptr_vaddr,
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(ulong)(bptr_vaddr + SIZE_BOOT_ENTRY));
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/* Wait a bit for the CPU to ack. */
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while ((__secondary_hold_acknowledge != hw_cpu) && (++n < 1000))
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mdelay(1);
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#else
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smp_generic_kick_cpu(nr);
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out_be64((u64 *)(bptr_vaddr + BOOT_ENTRY_ADDR_UPPER),
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__pa((u64)*((unsigned long long *) generic_secondary_smp_init)));
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if (!ioremappable)
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flush_dcache_range((ulong)bptr_vaddr,
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(ulong)(bptr_vaddr + SIZE_BOOT_ENTRY));
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#endif
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local_irq_restore(flags);
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if (ioremappable)
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iounmap(bptr_vaddr);
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pr_debug("waited %d msecs for CPU #%d.\n", n, nr);
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return 0;
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}
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struct smp_ops_t smp_85xx_ops = {
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.kick_cpu = smp_85xx_kick_cpu,
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#ifdef CONFIG_KEXEC
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.give_timebase = smp_generic_give_timebase,
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.take_timebase = smp_generic_take_timebase,
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#endif
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};
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#ifdef CONFIG_KEXEC
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atomic_t kexec_down_cpus = ATOMIC_INIT(0);
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void mpc85xx_smp_kexec_cpu_down(int crash_shutdown, int secondary)
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{
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local_irq_disable();
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if (secondary) {
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atomic_inc(&kexec_down_cpus);
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/* loop forever */
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while (1);
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}
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}
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static void mpc85xx_smp_kexec_down(void *arg)
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{
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if (ppc_md.kexec_cpu_down)
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ppc_md.kexec_cpu_down(0,1);
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}
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static void map_and_flush(unsigned long paddr)
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{
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struct page *page = pfn_to_page(paddr >> PAGE_SHIFT);
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unsigned long kaddr = (unsigned long)kmap(page);
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flush_dcache_range(kaddr, kaddr + PAGE_SIZE);
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kunmap(page);
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}
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/**
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* Before we reset the other cores, we need to flush relevant cache
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* out to memory so we don't get anything corrupted, some of these flushes
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* are performed out of an overabundance of caution as interrupts are not
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* disabled yet and we can switch cores
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*/
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static void mpc85xx_smp_flush_dcache_kexec(struct kimage *image)
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{
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kimage_entry_t *ptr, entry;
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unsigned long paddr;
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int i;
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if (image->type == KEXEC_TYPE_DEFAULT) {
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/* normal kexec images are stored in temporary pages */
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for (ptr = &image->head; (entry = *ptr) && !(entry & IND_DONE);
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ptr = (entry & IND_INDIRECTION) ?
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phys_to_virt(entry & PAGE_MASK) : ptr + 1) {
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if (!(entry & IND_DESTINATION)) {
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map_and_flush(entry);
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}
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}
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/* flush out last IND_DONE page */
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map_and_flush(entry);
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} else {
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/* crash type kexec images are copied to the crash region */
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for (i = 0; i < image->nr_segments; i++) {
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struct kexec_segment *seg = &image->segment[i];
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for (paddr = seg->mem; paddr < seg->mem + seg->memsz;
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paddr += PAGE_SIZE) {
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map_and_flush(paddr);
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}
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}
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}
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/* also flush the kimage struct to be passed in as well */
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flush_dcache_range((unsigned long)image,
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(unsigned long)image + sizeof(*image));
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}
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static void mpc85xx_smp_machine_kexec(struct kimage *image)
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{
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int timeout = INT_MAX;
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int i, num_cpus = num_present_cpus();
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mpc85xx_smp_flush_dcache_kexec(image);
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if (image->type == KEXEC_TYPE_DEFAULT)
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smp_call_function(mpc85xx_smp_kexec_down, NULL, 0);
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while ( (atomic_read(&kexec_down_cpus) != (num_cpus - 1)) &&
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( timeout > 0 ) )
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{
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timeout--;
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}
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if ( !timeout )
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printk(KERN_ERR "Unable to bring down secondary cpu(s)");
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for_each_online_cpu(i)
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{
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if ( i == smp_processor_id() ) continue;
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mpic_reset_core(i);
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}
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default_machine_kexec(image);
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}
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#endif /* CONFIG_KEXEC */
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static void __init
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smp_85xx_setup_cpu(int cpu_nr)
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{
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if (smp_85xx_ops.probe == smp_mpic_probe)
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mpic_setup_this_cpu();
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if (cpu_has_feature(CPU_FTR_DBELL))
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doorbell_setup_this_cpu();
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}
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void __init mpc85xx_smp_init(void)
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{
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struct device_node *np;
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smp_85xx_ops.setup_cpu = smp_85xx_setup_cpu;
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np = of_find_node_by_type(NULL, "open-pic");
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if (np) {
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smp_85xx_ops.probe = smp_mpic_probe;
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smp_85xx_ops.message_pass = smp_mpic_message_pass;
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}
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if (cpu_has_feature(CPU_FTR_DBELL)) {
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/*
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* If left NULL, .message_pass defaults to
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* smp_muxed_ipi_message_pass
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*/
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smp_85xx_ops.message_pass = NULL;
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smp_85xx_ops.cause_ipi = doorbell_cause_ipi;
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}
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smp_ops = &smp_85xx_ops;
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#ifdef CONFIG_KEXEC
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ppc_md.kexec_cpu_down = mpc85xx_smp_kexec_cpu_down;
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ppc_md.machine_kexec = mpc85xx_smp_machine_kexec;
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#endif
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}
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