90 lines
2.5 KiB
C
90 lines
2.5 KiB
C
/*
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* MX3 CPU type detection
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*
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* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/iim.h>
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unsigned int mx31_cpu_rev;
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EXPORT_SYMBOL(mx31_cpu_rev);
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struct mx3_cpu_type {
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u8 srev;
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const char *name;
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const char *v;
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unsigned int rev;
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};
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static struct mx3_cpu_type mx31_cpu_type[] __initdata = {
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{ .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = IMX_CHIP_REVISION_1_0 },
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{ .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
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{ .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
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{ .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 },
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{ .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 },
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{ .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 },
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{ .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 },
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{ .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 },
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{ .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 },
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};
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void __init mx31_read_cpu_rev(void)
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{
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u32 i, srev;
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/* read SREV register from IIM module */
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srev = __raw_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV));
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for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
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if (srev == mx31_cpu_type[i].srev) {
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printk(KERN_INFO
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"CPU identified as %s, silicon rev %s\n",
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mx31_cpu_type[i].name, mx31_cpu_type[i].v);
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mx31_cpu_rev = mx31_cpu_type[i].rev;
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return;
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}
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mx31_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
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printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
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}
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unsigned int mx35_cpu_rev;
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EXPORT_SYMBOL(mx35_cpu_rev);
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void __init mx35_read_cpu_rev(void)
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{
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u32 rev;
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char *srev;
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rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
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switch (rev) {
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case 0x00:
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mx35_cpu_rev = IMX_CHIP_REVISION_1_0;
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srev = "1.0";
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break;
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case 0x10:
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mx35_cpu_rev = IMX_CHIP_REVISION_2_0;
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srev = "2.0";
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break;
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case 0x11:
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mx35_cpu_rev = IMX_CHIP_REVISION_2_1;
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srev = "2.1";
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break;
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default:
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mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
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srev = "unknown";
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}
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printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
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}
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