174 lines
3.6 KiB
ArmAsm
174 lines
3.6 KiB
ArmAsm
/* arch/sparc64/kernel/ktlb.S: Kernel mapping TLB miss handling.
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*
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* Copyright (C) 1995, 1997, 2005 David S. Miller <davem@davemloft.net>
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* Copyright (C) 1996 Eddie C. Dost (ecd@brainaid.de)
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* Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
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* Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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*/
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#include <linux/config.h>
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#include <asm/head.h>
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#include <asm/asi.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/tsb.h>
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.text
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.align 32
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.globl kvmap_itlb
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kvmap_itlb:
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/* g6: TAG TARGET */
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mov TLB_TAG_ACCESS, %g4
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ldxa [%g4] ASI_IMMU, %g4
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kvmap_itlb_nonlinear:
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/* Catch kernel NULL pointer calls. */
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sethi %hi(PAGE_SIZE), %g5
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cmp %g4, %g5
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bleu,pn %xcc, kvmap_dtlb_longpath
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nop
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KERN_TSB_LOOKUP_TL1(%g4, %g6, %g5, %g1, %g2, %g3, kvmap_itlb_load)
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kvmap_itlb_tsb_miss:
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sethi %hi(LOW_OBP_ADDRESS), %g5
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cmp %g4, %g5
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blu,pn %xcc, kvmap_itlb_vmalloc_addr
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mov 0x1, %g5
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sllx %g5, 32, %g5
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cmp %g4, %g5
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blu,pn %xcc, kvmap_itlb_obp
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nop
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kvmap_itlb_vmalloc_addr:
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KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_itlb_longpath)
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TSB_LOCK_TAG(%g1, %g2, %g4)
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/* Load and check PTE. */
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ldxa [%g5] ASI_PHYS_USE_EC, %g5
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brgez,a,pn %g5, kvmap_itlb_longpath
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stx %g0, [%g1]
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TSB_WRITE(%g1, %g5, %g6)
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/* fallthrough to TLB load */
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kvmap_itlb_load:
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stxa %g5, [%g0] ASI_ITLB_DATA_IN ! Reload TLB
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retry
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kvmap_itlb_longpath:
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rdpr %pstate, %g5
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wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
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rdpr %tpc, %g5
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ba,pt %xcc, sparc64_realfault_common
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mov FAULT_CODE_ITLB, %g4
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kvmap_itlb_obp:
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OBP_TRANS_LOOKUP(%g4, %g5, %g2, %g3, kvmap_itlb_longpath)
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TSB_LOCK_TAG(%g1, %g2, %g4)
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TSB_WRITE(%g1, %g5, %g6)
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ba,pt %xcc, kvmap_itlb_load
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nop
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kvmap_dtlb_obp:
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OBP_TRANS_LOOKUP(%g4, %g5, %g2, %g3, kvmap_dtlb_longpath)
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TSB_LOCK_TAG(%g1, %g2, %g4)
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TSB_WRITE(%g1, %g5, %g6)
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ba,pt %xcc, kvmap_dtlb_load
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nop
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.align 32
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.globl kvmap_dtlb
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kvmap_dtlb:
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/* %g6: TAG TARGET */
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mov TLB_TAG_ACCESS, %g4
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ldxa [%g4] ASI_DMMU, %g4
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brgez,pn %g4, kvmap_dtlb_nonlinear
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nop
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#define KERN_HIGHBITS ((_PAGE_VALID|_PAGE_SZ4MB)^0xfffff80000000000)
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#define KERN_LOWBITS (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W)
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sethi %uhi(KERN_HIGHBITS), %g2
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or %g2, %ulo(KERN_HIGHBITS), %g2
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sllx %g2, 32, %g2
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or %g2, KERN_LOWBITS, %g2
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#undef KERN_HIGHBITS
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#undef KERN_LOWBITS
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.globl kvmap_linear_patch
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kvmap_linear_patch:
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ba,pt %xcc, kvmap_dtlb_load
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xor %g2, %g4, %g5
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kvmap_dtlb_vmalloc_addr:
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KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_dtlb_longpath)
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TSB_LOCK_TAG(%g1, %g2, %g4)
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/* Load and check PTE. */
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ldxa [%g5] ASI_PHYS_USE_EC, %g5
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brgez,a,pn %g5, kvmap_dtlb_longpath
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stx %g0, [%g1]
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TSB_WRITE(%g1, %g5, %g6)
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/* fallthrough to TLB load */
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kvmap_dtlb_load:
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stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
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retry
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kvmap_dtlb_nonlinear:
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/* Catch kernel NULL pointer derefs. */
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sethi %hi(PAGE_SIZE), %g5
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cmp %g4, %g5
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bleu,pn %xcc, kvmap_dtlb_longpath
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nop
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KERN_TSB_LOOKUP_TL1(%g4, %g6, %g5, %g1, %g2, %g3, kvmap_dtlb_load)
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kvmap_dtlb_tsbmiss:
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sethi %hi(MODULES_VADDR), %g5
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cmp %g4, %g5
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blu,pn %xcc, kvmap_dtlb_longpath
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mov (VMALLOC_END >> 24), %g5
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sllx %g5, 24, %g5
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cmp %g4, %g5
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bgeu,pn %xcc, kvmap_dtlb_longpath
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nop
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kvmap_check_obp:
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sethi %hi(LOW_OBP_ADDRESS), %g5
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cmp %g4, %g5
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blu,pn %xcc, kvmap_dtlb_vmalloc_addr
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mov 0x1, %g5
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sllx %g5, 32, %g5
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cmp %g4, %g5
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blu,pn %xcc, kvmap_dtlb_obp
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nop
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ba,pt %xcc, kvmap_dtlb_vmalloc_addr
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nop
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kvmap_dtlb_longpath:
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rdpr %pstate, %g5
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wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
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rdpr %tl, %g4
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cmp %g4, 1
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mov TLB_TAG_ACCESS, %g4
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ldxa [%g4] ASI_DMMU, %g5
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be,pt %xcc, sparc64_realfault_common
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mov FAULT_CODE_DTLB, %g4
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ba,pt %xcc, winfix_trampoline
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nop
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