125 lines
5.9 KiB
C
125 lines
5.9 KiB
C
/*
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* File: include/asm-blackfin/mach-bf538/anomaly.h
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* Copyright (C) 2004-2008 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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/* This file shoule be up to date with:
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* - Revision F, 06/18/2008; ADSP-BF538/BF538F Blackfin Processor Anomaly List
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* - Revision K, 06/18/2008; ADSP-BF539/BF539F Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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#define _MACH_ANOMALY_H_
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#if __SILICON_REVISION__ < 4
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# error will not work on BF538 silicon version 0.0, 0.1, 0.2, or 0.3
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#endif
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
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#define ANOMALY_05000074 (1)
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/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
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#define ANOMALY_05000119 (1)
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/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
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#define ANOMALY_05000122 (1)
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/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
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#define ANOMALY_05000166 (1)
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/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
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#define ANOMALY_05000179 (1)
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/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
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#define ANOMALY_05000180 (1)
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/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
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#define ANOMALY_05000193 (1)
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/* Current DMA Address Shows Wrong Value During Carry Fix */
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#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
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/* NMI Event at Boot Time Results in Unpredictable State */
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#define ANOMALY_05000219 (1)
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/* SPI Slave Boot Mode Modifies Registers from Reset Value */
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#define ANOMALY_05000229 (1)
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/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
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#define ANOMALY_05000233 (1)
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/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */
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#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
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/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
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#define ANOMALY_05000245 (1)
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/* Maximum External Clock Speed for Timers */
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#define ANOMALY_05000253 (1)
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/* DCPLB_FAULT_ADDR MMR register may be corrupted */
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#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
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/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
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#define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
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/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
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#define ANOMALY_05000272 (1)
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/* Writes to Synchronous SDRAM Memory May Be Lost */
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#define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
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/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
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#define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
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/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
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#define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
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/* False Hardware Error Exception when ISR Context Is Not Restored */
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#define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
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/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
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#define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
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/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
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#define ANOMALY_05000283 (__SILICON_REVISION__ < 4)
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/* SPORTs May Receive Bad Data If FIFOs Fill Up */
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#define ANOMALY_05000288 (__SILICON_REVISION__ < 4)
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/* Reads from CAN Mailbox and Acceptance Mask Area Can Fail */
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#define ANOMALY_05000291 (__SILICON_REVISION__ < 4)
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/* Hibernate Leakage Current Is Higher Than Specified */
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#define ANOMALY_05000293 (__SILICON_REVISION__ < 4)
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/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
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#define ANOMALY_05000294 (1)
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/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
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#define ANOMALY_05000301 (__SILICON_REVISION__ < 4)
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/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
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#define ANOMALY_05000304 (__SILICON_REVISION__ < 4)
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/* SCKELOW Bit Does Not Maintain State Through Hibernate */
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#define ANOMALY_05000307 (__SILICON_REVISION__ < 4)
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/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
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#define ANOMALY_05000310 (1)
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/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
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#define ANOMALY_05000312 (__SILICON_REVISION__ < 5)
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/* PPI Is Level-Sensitive on First Transfer */
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#define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
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/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
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#define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
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/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
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#define ANOMALY_05000318 (__SILICON_REVISION__ < 4)
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/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
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#define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
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/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
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#define ANOMALY_05000357 (__SILICON_REVISION__ < 5)
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/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
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#define ANOMALY_05000366 (1)
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
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#define ANOMALY_05000371 (__SILICON_REVISION__ < 5)
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/* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */
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#define ANOMALY_05000374 (__SILICON_REVISION__ == 4)
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/* New Feature: Open-Drain GPIO Outputs on PC1 and PC4 (Not Available on Older Silicon) */
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#define ANOMALY_05000375 (__SILICON_REVISION__ < 4)
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/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
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#define ANOMALY_05000402 (__SILICON_REVISION__ < 4)
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/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
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#define ANOMALY_05000403 (1)
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/* Speculative Fetches Can Cause Undesired External FIFO Operations */
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#define ANOMALY_05000416 (1)
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/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
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#define ANOMALY_05000443 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000158 (0)
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#define ANOMALY_05000198 (0)
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#define ANOMALY_05000230 (0)
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#define ANOMALY_05000263 (0)
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#define ANOMALY_05000311 (0)
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#define ANOMALY_05000323 (0)
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#define ANOMALY_05000353 (1)
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#define ANOMALY_05000363 (0)
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#define ANOMALY_05000386 (1)
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#define ANOMALY_05000435 (0)
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#endif
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