212 lines
7.1 KiB
C
212 lines
7.1 KiB
C
/*
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* file: include/asm-blackfin/mach-bf538/irq.h
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* based on: include/asm-blackfin/mach-bf537/irq.h
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* author: Michael Hennerich (michael.hennerich@analog.com)
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*
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* created:
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* description:
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* system mmr register map
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* rev:
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*
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* modified:
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*
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*
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* bugs: enter bugs at http://blackfin.uclinux.org/
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*
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* this program is free software; you can redistribute it and/or modify
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* it under the terms of the gnu general public license as published by
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* the free software foundation; either version 2, or (at your option)
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* any later version.
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*
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* this program is distributed in the hope that it will be useful,
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* but without any warranty; without even the implied warranty of
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* merchantability or fitness for a particular purpose. see the
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* gnu general public license for more details.
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*
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* you should have received a copy of the gnu general public license
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* along with this program; see the file copying.
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* if not, write to the free software foundation,
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* 59 temple place - suite 330, boston, ma 02111-1307, usa.
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*/
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#ifndef _BF538_IRQ_H_
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#define _BF538_IRQ_H_
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/*
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* Interrupt source definitions
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Event Source Core Event Name
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Core Emulation **
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Events (highest priority) EMU 0
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Reset RST 1
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NMI NMI 2
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Exception EVX 3
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Reserved -- 4
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Hardware Error IVHW 5
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Core Timer IVTMR 6 *
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.....
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Software Interrupt 1 IVG14 31
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Software Interrupt 2 --
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(lowest priority) IVG15 32 *
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*/
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#define NR_PERI_INTS (2 * 32)
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/* The ABSTRACT IRQ definitions */
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/** the first seven of the following are fixed, the rest you change if you need to **/
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#define IRQ_EMU 0 /* Emulation */
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#define IRQ_RST 1 /* reset */
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#define IRQ_NMI 2 /* Non Maskable */
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#define IRQ_EVX 3 /* Exception */
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#define IRQ_UNUSED 4 /* - unused interrupt */
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#define IRQ_HWERR 5 /* Hardware Error */
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#define IRQ_CORETMR 6 /* Core timer */
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#define BFIN_IRQ(x) ((x) + 7)
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#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
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#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
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#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error */
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#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Status */
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#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Status */
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#define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status */
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#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status */
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#define IRQ_RTC BFIN_IRQ(7) /* RTC */
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#define IRQ_PPI BFIN_IRQ(8) /* DMA Channel 0 (PPI) */
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#define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA 1 Channel (SPORT0 RX) */
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#define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA 2 Channel (SPORT0 TX) */
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#define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA 3 Channel (SPORT1 RX) */
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#define IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA 4 Channel (SPORT1 TX) */
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#define IRQ_SPI0 BFIN_IRQ(13) /* DMA 5 Channel (SPI0) */
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#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA 6 Channel (UART0 RX) */
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#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA 7 Channel (UART0 TX) */
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#define IRQ_TMR0 BFIN_IRQ(16) /* Timer 0 */
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#define IRQ_TMR1 BFIN_IRQ(17) /* Timer 1 */
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#define IRQ_TMR2 BFIN_IRQ(18) /* Timer 2 */
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#define IRQ_PORTF_INTA BFIN_IRQ(19) /* Port F Interrupt A */
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#define IRQ_PORTF_INTB BFIN_IRQ(20) /* Port F Interrupt B */
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#define IRQ_MEM0_DMA0 BFIN_IRQ(21) /* MDMA0 Stream 0 */
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#define IRQ_MEM0_DMA1 BFIN_IRQ(22) /* MDMA0 Stream 1 */
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#define IRQ_WATCH BFIN_IRQ(23) /* Software Watchdog Timer */
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#define IRQ_DMA1_ERROR BFIN_IRQ(24) /* DMA Error 1 (generic) */
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#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Status */
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#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Status */
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#define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status */
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#define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status */
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#define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status */
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#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status */
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#define IRQ_CAN_ERROR BFIN_IRQ(32) /* CAN Status (Error) Interrupt */
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#define IRQ_SPORT2_RX BFIN_IRQ(33) /* DMA 8 Channel (SPORT2 RX) */
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#define IRQ_SPORT2_TX BFIN_IRQ(34) /* DMA 9 Channel (SPORT2 TX) */
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#define IRQ_SPORT3_RX BFIN_IRQ(35) /* DMA 10 Channel (SPORT3 RX) */
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#define IRQ_SPORT3_TX BFIN_IRQ(36) /* DMA 11 Channel (SPORT3 TX) */
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#define IRQ_SPI1 BFIN_IRQ(39) /* DMA 14 Channel (SPI1) */
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#define IRQ_SPI2 BFIN_IRQ(40) /* DMA 15 Channel (SPI2) */
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#define IRQ_UART1_RX BFIN_IRQ(41) /* DMA 16 Channel (UART1 RX) */
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#define IRQ_UART1_TX BFIN_IRQ(42) /* DMA 17 Channel (UART1 TX) */
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#define IRQ_UART2_RX BFIN_IRQ(43) /* DMA 18 Channel (UART2 RX) */
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#define IRQ_UART2_TX BFIN_IRQ(44) /* DMA 19 Channel (UART2 TX) */
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#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 */
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#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 */
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#define IRQ_CAN_RX BFIN_IRQ(47) /* CAN Receive Interrupt */
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#define IRQ_CAN_TX BFIN_IRQ(48) /* CAN Transmit Interrupt */
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#define IRQ_MEM1_DMA0 BFIN_IRQ(49) /* MDMA1 Stream 0 */
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#define IRQ_MEM1_DMA1 BFIN_IRQ(50) /* MDMA1 Stream 1 */
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#define SYS_IRQS BFIN_IRQ(63) /* 70 */
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#define IRQ_PF0 71
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#define IRQ_PF1 72
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#define IRQ_PF2 73
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#define IRQ_PF3 74
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#define IRQ_PF4 75
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#define IRQ_PF5 76
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#define IRQ_PF6 77
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#define IRQ_PF7 78
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#define IRQ_PF8 79
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#define IRQ_PF9 80
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#define IRQ_PF10 81
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#define IRQ_PF11 82
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#define IRQ_PF12 83
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#define IRQ_PF13 84
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#define IRQ_PF14 85
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#define IRQ_PF15 86
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#define GPIO_IRQ_BASE IRQ_PF0
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#define NR_IRQS (IRQ_PF15+1)
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#define IVG7 7
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#define IVG8 8
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#define IVG9 9
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#define IVG10 10
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#define IVG11 11
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#define IVG12 12
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#define IVG13 13
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#define IVG14 14
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#define IVG15 15
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/* IAR0 BIT FIELDS */
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#define IRQ_PLL_WAKEUP_POS 0
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#define IRQ_DMA0_ERROR_POS 4
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#define IRQ_PPI_ERROR_POS 8
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#define IRQ_SPORT0_ERROR_POS 12
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#define IRQ_SPORT1_ERROR_POS 16
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#define IRQ_SPI0_ERROR_POS 20
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#define IRQ_UART0_ERROR_POS 24
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#define IRQ_RTC_POS 28
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/* IAR1 BIT FIELDS */
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#define IRQ_PPI_POS 0
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#define IRQ_SPORT0_RX_POS 4
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#define IRQ_SPORT0_TX_POS 8
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#define IRQ_SPORT1_RX_POS 12
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#define IRQ_SPORT1_TX_POS 16
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#define IRQ_SPI0_POS 20
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#define IRQ_UART0_RX_POS 24
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#define IRQ_UART0_TX_POS 28
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/* IAR2 BIT FIELDS */
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#define IRQ_TMR0_POS 0
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#define IRQ_TMR1_POS 4
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#define IRQ_TMR2_POS 8
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#define IRQ_PORTF_INTA_POS 12
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#define IRQ_PORTF_INTB_POS 16
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#define IRQ_MEM0_DMA0_POS 20
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#define IRQ_MEM0_DMA1_POS 24
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#define IRQ_WATCH_POS 28
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/* IAR3 BIT FIELDS */
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#define IRQ_DMA1_ERROR_POS 0
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#define IRQ_SPORT2_ERROR_POS 4
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#define IRQ_SPORT3_ERROR_POS 8
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#define IRQ_SPI1_ERROR_POS 16
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#define IRQ_SPI2_ERROR_POS 20
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#define IRQ_UART1_ERROR_POS 24
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#define IRQ_UART2_ERROR_POS 28
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/* IAR4 BIT FIELDS */
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#define IRQ_CAN_ERROR_POS 0
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#define IRQ_SPORT2_RX_POS 4
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#define IRQ_SPORT2_TX_POS 8
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#define IRQ_SPORT3_RX_POS 12
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#define IRQ_SPORT3_TX_POS 16
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#define IRQ_SPI1_POS 28
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/* IAR5 BIT FIELDS */
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#define IRQ_SPI2_POS 0
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#define IRQ_UART1_RX_POS 4
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#define IRQ_UART1_TX_POS 8
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#define IRQ_UART2_RX_POS 12
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#define IRQ_UART2_TX_POS 16
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#define IRQ_TWI0_POS 20
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#define IRQ_TWI1_POS 24
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#define IRQ_CAN_RX_POS 28
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/* IAR6 BIT FIELDS */
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#define IRQ_CAN_TX_POS 0
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#define IRQ_MEM1_DMA0_POS 4
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#define IRQ_MEM1_DMA1_POS 8
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#endif /* _BF538_IRQ_H_ */
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