122 lines
2.9 KiB
ArmAsm
122 lines
2.9 KiB
ArmAsm
/*
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* include/asm-arm/arch-s3c2410/entry-macro.S
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*
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* Low-level IRQ helper macros for S3C2410-based platforms
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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* Modifications:
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* 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
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*/
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#include <asm/hardware.h>
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#include <asm/arch/irqs.h>
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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mov \tmp, #S3C24XX_VA_IRQ
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ldr \irqnr, [ \tmp, #0x14 ] @ get irq no
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30000:
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teq \irqnr, #4
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teqne \irqnr, #5
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beq 1002f @ external irq reg
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@ debug check to see if interrupt reported is the same
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@ as the offset....
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teq \irqnr, #0
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beq 20002f
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ldr \irqstat, [ \tmp, #0x10 ] @ INTPND
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mov \irqstat, \irqstat, lsr \irqnr
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tst \irqstat, #1
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bne 20002f
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/* debug/warning if we get an invalud response from the
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* INTOFFSET register */
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#if 1
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stmfd r13!, { r0 - r4 , r8-r12, r14 }
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ldr r1, [ \tmp, #0x14 ] @ INTOFFSET
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ldr r2, [ \tmp, #0x10 ] @ INTPND
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ldr r3, [ \tmp, #0x00 ] @ SRCPND
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adr r0, 20003f
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bl printk
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b 20004f
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20003:
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.ascii "<7>irq: err - bad offset %d, intpnd=%08x, srcpnd=%08x\n"
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.byte 0
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.align 4
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20004:
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mov r1, #1
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mov \tmp, #S3C24XX_VA_IRQ
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ldmfd r13!, { r0 - r4 , r8-r12, r14 }
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#endif
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@ try working out interrupt number for ourselves
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mov \irqnr, #0
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ldr \irqstat, [ \tmp, #0x10 ] @ INTPND
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10021:
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movs \irqstat, \irqstat, lsr#1
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bcs 30000b @ try and re-start the proccess
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add \irqnr, \irqnr, #1
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cmp \irqnr, #32
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ble 10021b
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@ found no interrupt, set Z flag and leave
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movs \irqnr, #0
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b 1001f
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20005:
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20002: @ exit
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@ we base the s3c2410x interrupts at 16 and above to allow
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@ isa peripherals to have their standard interrupts, also
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@ ensure that Z flag is un-set on exit
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@ note, we cannot be sure if we get IRQ_EINT0 (0) that
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@ there is simply no interrupt pending, so in all other
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@ cases we jump to say we have found something, otherwise
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@ we check to see if the interrupt really is assrted
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adds \irqnr, \irqnr, #IRQ_EINT0
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teq \irqnr, #IRQ_EINT0
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bne 1001f @ exit
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ldr \irqstat, [ \tmp, #0x10 ] @ INTPND
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teq \irqstat, #0
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moveq \irqnr, #0
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b 1001f
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@ we get here from no main or external interrupts pending
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1002:
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add \tmp, \tmp, #S3C24XX_VA_GPIO - S3C24XX_VA_IRQ
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ldr \irqstat, [ \tmp, # 0xa8 ] @ EXTINTPEND
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ldr \irqnr, [ \tmp, # 0xa4 ] @ EXTINTMASK
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bic \irqstat, \irqstat, \irqnr @ clear masked irqs
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mov \irqnr, #IRQ_EINT4 @ start extint nos
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mov \irqstat, \irqstat, lsr#4 @ ignore bottom 4 bits
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10021:
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movs \irqstat, \irqstat, lsr#1
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bcs 1004f
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add \irqnr, \irqnr, #1
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cmp \irqnr, #IRQ_EINT23
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ble 10021b
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@ found no interrupt, set Z flag and leave
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movs \irqnr, #0
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1004: @ ensure Z flag clear in case our MOVS shifted out the last bit
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teq \irqnr, #0
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1001:
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@ exit irq routine
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.endm
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/* currently don't need an disable_fiq macro */
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.macro disable_fiq
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.endm
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