279 lines
9.1 KiB
C
279 lines
9.1 KiB
C
#ifndef __iop_fifo_out_defs_h
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#define __iop_fifo_out_defs_h
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/*
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* This file is autogenerated from
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* file: ../../inst/io_proc/rtl/iop_fifo_out.r
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* id: <not found>
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* last modfied: Mon Apr 11 16:10:09 2005
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*
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* by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_defs.h ../../inst/io_proc/rtl/iop_fifo_out.r
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* id: $Id: iop_fifo_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
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* Any changes here will be lost.
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*
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* -*- buffer-read-only: t -*-
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*/
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/* Main access macros */
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#ifndef REG_RD
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#define REG_RD( scope, inst, reg ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR
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#define REG_WR( scope, inst, reg, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_VECT
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#define REG_RD_VECT( scope, inst, reg, index ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_VECT
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#define REG_WR_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT
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#define REG_RD_INT( scope, inst, reg ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT
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#define REG_WR_INT( scope, inst, reg, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT_VECT
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#define REG_RD_INT_VECT( scope, inst, reg, index ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT_VECT
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#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_TYPE_CONV
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#define REG_TYPE_CONV( type, orgtype, val ) \
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( { union { orgtype o; type n; } r; r.o = val; r.n; } )
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#endif
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#ifndef reg_page_size
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#define reg_page_size 8192
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#endif
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#ifndef REG_ADDR
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#define REG_ADDR( scope, inst, reg ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_ADDR_VECT
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#define REG_ADDR_VECT( scope, inst, reg, index ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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/* C-code for register scope iop_fifo_out */
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/* Register rw_cfg, scope iop_fifo_out, type rw */
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typedef struct {
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unsigned int free_lim : 3;
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unsigned int byte_order : 2;
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unsigned int trig : 2;
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unsigned int last_dis_dif_in : 1;
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unsigned int mode : 2;
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unsigned int delay_out_last : 1;
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unsigned int last_dis_dif_out : 1;
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unsigned int dummy1 : 20;
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} reg_iop_fifo_out_rw_cfg;
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#define REG_RD_ADDR_iop_fifo_out_rw_cfg 0
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#define REG_WR_ADDR_iop_fifo_out_rw_cfg 0
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/* Register rw_ctrl, scope iop_fifo_out, type rw */
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typedef struct {
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unsigned int dif_in_en : 1;
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unsigned int dif_out_en : 1;
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unsigned int dummy1 : 30;
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} reg_iop_fifo_out_rw_ctrl;
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#define REG_RD_ADDR_iop_fifo_out_rw_ctrl 4
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#define REG_WR_ADDR_iop_fifo_out_rw_ctrl 4
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/* Register r_stat, scope iop_fifo_out, type r */
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typedef struct {
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unsigned int avail_bytes : 4;
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unsigned int last : 8;
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unsigned int dif_in_en : 1;
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unsigned int dif_out_en : 1;
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unsigned int zero_data_last : 1;
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unsigned int dummy1 : 17;
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} reg_iop_fifo_out_r_stat;
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#define REG_RD_ADDR_iop_fifo_out_r_stat 8
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/* Register rw_wr1byte, scope iop_fifo_out, type rw */
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typedef struct {
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unsigned int data : 8;
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unsigned int dummy1 : 24;
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} reg_iop_fifo_out_rw_wr1byte;
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#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte 12
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#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte 12
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/* Register rw_wr2byte, scope iop_fifo_out, type rw */
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typedef struct {
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unsigned int data : 16;
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unsigned int dummy1 : 16;
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} reg_iop_fifo_out_rw_wr2byte;
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#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte 16
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#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte 16
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/* Register rw_wr3byte, scope iop_fifo_out, type rw */
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typedef struct {
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unsigned int data : 24;
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unsigned int dummy1 : 8;
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} reg_iop_fifo_out_rw_wr3byte;
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#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte 20
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#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte 20
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/* Register rw_wr4byte, scope iop_fifo_out, type rw */
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typedef struct {
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unsigned int data : 32;
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} reg_iop_fifo_out_rw_wr4byte;
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#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte 24
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#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte 24
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/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */
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typedef struct {
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unsigned int data : 8;
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unsigned int dummy1 : 24;
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} reg_iop_fifo_out_rw_wr1byte_last;
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#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte_last 28
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#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte_last 28
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/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */
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typedef struct {
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unsigned int data : 16;
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unsigned int dummy1 : 16;
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} reg_iop_fifo_out_rw_wr2byte_last;
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#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte_last 32
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#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte_last 32
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/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */
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typedef struct {
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unsigned int data : 24;
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unsigned int dummy1 : 8;
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} reg_iop_fifo_out_rw_wr3byte_last;
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#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte_last 36
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#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte_last 36
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/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */
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typedef struct {
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unsigned int data : 32;
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} reg_iop_fifo_out_rw_wr4byte_last;
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#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte_last 40
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#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte_last 40
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/* Register rw_set_last, scope iop_fifo_out, type rw */
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typedef unsigned int reg_iop_fifo_out_rw_set_last;
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#define REG_RD_ADDR_iop_fifo_out_rw_set_last 44
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#define REG_WR_ADDR_iop_fifo_out_rw_set_last 44
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/* Register rs_rd_data, scope iop_fifo_out, type rs */
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typedef unsigned int reg_iop_fifo_out_rs_rd_data;
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#define REG_RD_ADDR_iop_fifo_out_rs_rd_data 48
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/* Register r_rd_data, scope iop_fifo_out, type r */
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typedef unsigned int reg_iop_fifo_out_r_rd_data;
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#define REG_RD_ADDR_iop_fifo_out_r_rd_data 52
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/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */
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typedef unsigned int reg_iop_fifo_out_rw_strb_dif_out;
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#define REG_RD_ADDR_iop_fifo_out_rw_strb_dif_out 56
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#define REG_WR_ADDR_iop_fifo_out_rw_strb_dif_out 56
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/* Register rw_intr_mask, scope iop_fifo_out, type rw */
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typedef struct {
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unsigned int urun : 1;
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unsigned int last_data : 1;
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unsigned int dav : 1;
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unsigned int free : 1;
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unsigned int orun : 1;
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unsigned int dummy1 : 27;
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} reg_iop_fifo_out_rw_intr_mask;
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#define REG_RD_ADDR_iop_fifo_out_rw_intr_mask 60
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#define REG_WR_ADDR_iop_fifo_out_rw_intr_mask 60
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/* Register rw_ack_intr, scope iop_fifo_out, type rw */
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typedef struct {
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unsigned int urun : 1;
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unsigned int last_data : 1;
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unsigned int dav : 1;
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unsigned int free : 1;
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unsigned int orun : 1;
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unsigned int dummy1 : 27;
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} reg_iop_fifo_out_rw_ack_intr;
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#define REG_RD_ADDR_iop_fifo_out_rw_ack_intr 64
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#define REG_WR_ADDR_iop_fifo_out_rw_ack_intr 64
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/* Register r_intr, scope iop_fifo_out, type r */
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typedef struct {
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unsigned int urun : 1;
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unsigned int last_data : 1;
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unsigned int dav : 1;
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unsigned int free : 1;
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unsigned int orun : 1;
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unsigned int dummy1 : 27;
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} reg_iop_fifo_out_r_intr;
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#define REG_RD_ADDR_iop_fifo_out_r_intr 68
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/* Register r_masked_intr, scope iop_fifo_out, type r */
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typedef struct {
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unsigned int urun : 1;
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unsigned int last_data : 1;
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unsigned int dav : 1;
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unsigned int free : 1;
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unsigned int orun : 1;
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unsigned int dummy1 : 27;
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} reg_iop_fifo_out_r_masked_intr;
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#define REG_RD_ADDR_iop_fifo_out_r_masked_intr 72
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/* Constants */
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enum {
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regk_iop_fifo_out_hi = 0x00000000,
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regk_iop_fifo_out_neg = 0x00000002,
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regk_iop_fifo_out_no = 0x00000000,
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regk_iop_fifo_out_order16 = 0x00000001,
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regk_iop_fifo_out_order24 = 0x00000002,
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regk_iop_fifo_out_order32 = 0x00000003,
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regk_iop_fifo_out_order8 = 0x00000000,
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regk_iop_fifo_out_pos = 0x00000001,
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regk_iop_fifo_out_pos_neg = 0x00000003,
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regk_iop_fifo_out_rw_cfg_default = 0x00000024,
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regk_iop_fifo_out_rw_ctrl_default = 0x00000000,
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regk_iop_fifo_out_rw_intr_mask_default = 0x00000000,
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regk_iop_fifo_out_rw_set_last_default = 0x00000000,
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regk_iop_fifo_out_rw_strb_dif_out_default = 0x00000000,
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regk_iop_fifo_out_rw_wr1byte_default = 0x00000000,
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regk_iop_fifo_out_rw_wr1byte_last_default = 0x00000000,
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regk_iop_fifo_out_rw_wr2byte_default = 0x00000000,
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regk_iop_fifo_out_rw_wr2byte_last_default = 0x00000000,
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regk_iop_fifo_out_rw_wr3byte_default = 0x00000000,
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regk_iop_fifo_out_rw_wr3byte_last_default = 0x00000000,
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regk_iop_fifo_out_rw_wr4byte_default = 0x00000000,
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regk_iop_fifo_out_rw_wr4byte_last_default = 0x00000000,
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regk_iop_fifo_out_size16 = 0x00000002,
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regk_iop_fifo_out_size24 = 0x00000001,
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regk_iop_fifo_out_size32 = 0x00000000,
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regk_iop_fifo_out_size8 = 0x00000003,
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regk_iop_fifo_out_yes = 0x00000001
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};
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#endif /* __iop_fifo_out_defs_h */
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