678 lines
16 KiB
C
678 lines
16 KiB
C
/* linux/arch/arm/mach-s3c2410/pm.c
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*
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* Copyright (c) 2004 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2410 Power Manager (Suspend-To-RAM) support
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*
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* See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Parts based on arch/arm/mach-pxa/pm.c
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*
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* Thanks to Dimitry Andric for debugging
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*
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* Modifications:
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* 10-Mar-2005 LCVR Changed S3C2410_VA_UART to S3C24XX_VA_UART
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*/
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#include <linux/init.h>
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#include <linux/suspend.h>
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#include <linux/errno.h>
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#include <linux/time.h>
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#include <linux/interrupt.h>
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#include <linux/crc32.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/arch/regs-serial.h>
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#include <asm/arch/regs-clock.h>
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#include <asm/arch/regs-gpio.h>
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#include <asm/arch/regs-mem.h>
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#include <asm/arch/regs-irq.h>
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#include <asm/mach/time.h>
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#include "pm.h"
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/* for external use */
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unsigned long s3c_pm_flags;
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/* cache functions from arch/arm/mm/proc-arm920.S */
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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extern void arm920_flush_kern_cache_all(void);
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#else
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static void arm920_flush_kern_cache_all(void) { }
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#endif
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#define PFX "s3c24xx-pm: "
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static struct sleep_save core_save[] = {
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SAVE_ITEM(S3C2410_LOCKTIME),
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SAVE_ITEM(S3C2410_CLKCON),
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/* we restore the timings here, with the proviso that the board
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* brings the system up in an slower, or equal frequency setting
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* to the original system.
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*
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* if we cannot guarantee this, then things are going to go very
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* wrong here, as we modify the refresh and both pll settings.
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*/
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SAVE_ITEM(S3C2410_BWSCON),
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SAVE_ITEM(S3C2410_BANKCON0),
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SAVE_ITEM(S3C2410_BANKCON1),
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SAVE_ITEM(S3C2410_BANKCON2),
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SAVE_ITEM(S3C2410_BANKCON3),
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SAVE_ITEM(S3C2410_BANKCON4),
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SAVE_ITEM(S3C2410_BANKCON5),
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SAVE_ITEM(S3C2410_CLKDIVN),
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SAVE_ITEM(S3C2410_MPLLCON),
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SAVE_ITEM(S3C2410_UPLLCON),
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SAVE_ITEM(S3C2410_CLKSLOW),
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SAVE_ITEM(S3C2410_REFRESH),
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};
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/* this lot should be really saved by the IRQ code */
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static struct sleep_save irq_save[] = {
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SAVE_ITEM(S3C2410_EXTINT0),
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SAVE_ITEM(S3C2410_EXTINT1),
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SAVE_ITEM(S3C2410_EXTINT2),
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SAVE_ITEM(S3C2410_EINFLT0),
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SAVE_ITEM(S3C2410_EINFLT1),
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SAVE_ITEM(S3C2410_EINFLT2),
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SAVE_ITEM(S3C2410_EINFLT3),
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SAVE_ITEM(S3C2410_EINTMASK),
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SAVE_ITEM(S3C2410_INTMSK)
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};
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static struct sleep_save gpio_save[] = {
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SAVE_ITEM(S3C2410_GPACON),
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SAVE_ITEM(S3C2410_GPADAT),
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SAVE_ITEM(S3C2410_GPBCON),
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SAVE_ITEM(S3C2410_GPBDAT),
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SAVE_ITEM(S3C2410_GPBUP),
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SAVE_ITEM(S3C2410_GPCCON),
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SAVE_ITEM(S3C2410_GPCDAT),
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SAVE_ITEM(S3C2410_GPCUP),
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SAVE_ITEM(S3C2410_GPDCON),
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SAVE_ITEM(S3C2410_GPDDAT),
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SAVE_ITEM(S3C2410_GPDUP),
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SAVE_ITEM(S3C2410_GPECON),
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SAVE_ITEM(S3C2410_GPEDAT),
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SAVE_ITEM(S3C2410_GPEUP),
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SAVE_ITEM(S3C2410_GPFCON),
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SAVE_ITEM(S3C2410_GPFDAT),
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SAVE_ITEM(S3C2410_GPFUP),
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SAVE_ITEM(S3C2410_GPGCON),
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SAVE_ITEM(S3C2410_GPGDAT),
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SAVE_ITEM(S3C2410_GPGUP),
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SAVE_ITEM(S3C2410_GPHCON),
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SAVE_ITEM(S3C2410_GPHDAT),
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SAVE_ITEM(S3C2410_GPHUP),
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SAVE_ITEM(S3C2410_DCLKCON),
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};
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#ifdef CONFIG_S3C2410_PM_DEBUG
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#define SAVE_UART(va) \
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SAVE_ITEM((va) + S3C2410_ULCON), \
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SAVE_ITEM((va) + S3C2410_UCON), \
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SAVE_ITEM((va) + S3C2410_UFCON), \
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SAVE_ITEM((va) + S3C2410_UMCON), \
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SAVE_ITEM((va) + S3C2410_UBRDIV)
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static struct sleep_save uart_save[] = {
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SAVE_UART(S3C24XX_VA_UART0),
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SAVE_UART(S3C24XX_VA_UART1),
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#ifndef CONFIG_CPU_S3C2400
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SAVE_UART(S3C24XX_VA_UART2),
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#endif
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};
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/* debug
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*
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* we send the debug to printascii() to allow it to be seen if the
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* system never wakes up from the sleep
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*/
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extern void printascii(const char *);
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static void pm_dbg(const char *fmt, ...)
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{
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va_list va;
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char buff[256];
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va_start(va, fmt);
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vsprintf(buff, fmt, va);
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va_end(va);
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printascii(buff);
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}
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static void s3c2410_pm_debug_init(void)
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{
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unsigned long tmp = __raw_readl(S3C2410_CLKCON);
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/* re-start uart clocks */
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tmp |= S3C2410_CLKCON_UART0;
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tmp |= S3C2410_CLKCON_UART1;
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tmp |= S3C2410_CLKCON_UART2;
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__raw_writel(tmp, S3C2410_CLKCON);
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udelay(10);
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}
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#define DBG(fmt...) pm_dbg(fmt)
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#else
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#define DBG(fmt...) printk(KERN_DEBUG fmt)
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#define s3c2410_pm_debug_init() do { } while(0)
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static struct sleep_save uart_save[] = {};
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#endif
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#if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0
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/* suspend checking code...
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*
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* this next area does a set of crc checks over all the installed
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* memory, so the system can verify if the resume was ok.
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*
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* CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
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* increasing it will mean that the area corrupted will be less easy to spot,
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* and reducing the size will cause the CRC save area to grow
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*/
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#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024)
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static u32 crc_size; /* size needed for the crc block */
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static u32 *crcs; /* allocated over suspend/resume */
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typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);
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/* s3c2410_pm_run_res
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*
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* go thorugh the given resource list, and look for system ram
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*/
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static void s3c2410_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
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{
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while (ptr != NULL) {
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if (ptr->child != NULL)
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s3c2410_pm_run_res(ptr->child, fn, arg);
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if ((ptr->flags & IORESOURCE_MEM) &&
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strcmp(ptr->name, "System RAM") == 0) {
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DBG("Found system RAM at %08lx..%08lx\n",
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ptr->start, ptr->end);
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arg = (fn)(ptr, arg);
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}
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ptr = ptr->sibling;
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}
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}
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static void s3c2410_pm_run_sysram(run_fn_t fn, u32 *arg)
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{
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s3c2410_pm_run_res(&iomem_resource, fn, arg);
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}
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static u32 *s3c2410_pm_countram(struct resource *res, u32 *val)
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{
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u32 size = (u32)(res->end - res->start)+1;
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size += CHECK_CHUNKSIZE-1;
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size /= CHECK_CHUNKSIZE;
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DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size);
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*val += size * sizeof(u32);
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return val;
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}
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/* s3c2410_pm_prepare_check
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*
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* prepare the necessary information for creating the CRCs. This
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* must be done before the final save, as it will require memory
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* allocating, and thus touching bits of the kernel we do not
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* know about.
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*/
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static void s3c2410_pm_check_prepare(void)
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{
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crc_size = 0;
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s3c2410_pm_run_sysram(s3c2410_pm_countram, &crc_size);
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DBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size);
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crcs = kmalloc(crc_size+4, GFP_KERNEL);
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if (crcs == NULL)
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printk(KERN_ERR "Cannot allocated CRC save area\n");
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}
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static u32 *s3c2410_pm_makecheck(struct resource *res, u32 *val)
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{
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unsigned long addr, left;
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for (addr = res->start; addr < res->end;
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addr += CHECK_CHUNKSIZE) {
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left = res->end - addr;
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if (left > CHECK_CHUNKSIZE)
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left = CHECK_CHUNKSIZE;
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*val = crc32_le(~0, phys_to_virt(addr), left);
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val++;
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}
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return val;
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}
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/* s3c2410_pm_check_store
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*
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* compute the CRC values for the memory blocks before the final
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* sleep.
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*/
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static void s3c2410_pm_check_store(void)
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{
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if (crcs != NULL)
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s3c2410_pm_run_sysram(s3c2410_pm_makecheck, crcs);
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}
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/* in_region
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*
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* return TRUE if the area defined by ptr..ptr+size contatins the
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* what..what+whatsz
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*/
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static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
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{
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if ((what+whatsz) < ptr)
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return 0;
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if (what > (ptr+size))
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return 0;
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return 1;
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}
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static u32 *s3c2410_pm_runcheck(struct resource *res, u32 *val)
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{
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void *save_at = phys_to_virt(s3c2410_sleep_save_phys);
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unsigned long addr;
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unsigned long left;
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void *ptr;
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u32 calc;
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for (addr = res->start; addr < res->end;
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addr += CHECK_CHUNKSIZE) {
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left = res->end - addr;
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if (left > CHECK_CHUNKSIZE)
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left = CHECK_CHUNKSIZE;
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ptr = phys_to_virt(addr);
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if (in_region(ptr, left, crcs, crc_size)) {
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DBG("skipping %08lx, has crc block in\n", addr);
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goto skip_check;
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}
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if (in_region(ptr, left, save_at, 32*4 )) {
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DBG("skipping %08lx, has save block in\n", addr);
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goto skip_check;
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}
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/* calculate and check the checksum */
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calc = crc32_le(~0, ptr, left);
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if (calc != *val) {
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printk(KERN_ERR PFX "Restore CRC error at "
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"%08lx (%08x vs %08x)\n", addr, calc, *val);
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DBG("Restore CRC error at %08lx (%08x vs %08x)\n",
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addr, calc, *val);
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}
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skip_check:
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val++;
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}
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return val;
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}
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/* s3c2410_pm_check_restore
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*
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* check the CRCs after the restore event and free the memory used
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* to hold them
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*/
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static void s3c2410_pm_check_restore(void)
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{
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if (crcs != NULL) {
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s3c2410_pm_run_sysram(s3c2410_pm_runcheck, crcs);
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kfree(crcs);
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crcs = NULL;
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}
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}
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#else
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#define s3c2410_pm_check_prepare() do { } while(0)
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#define s3c2410_pm_check_restore() do { } while(0)
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#define s3c2410_pm_check_store() do { } while(0)
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#endif
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/* helper functions to save and restore register state */
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void s3c2410_pm_do_save(struct sleep_save *ptr, int count)
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{
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for (; count > 0; count--, ptr++) {
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ptr->val = __raw_readl(ptr->reg);
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DBG("saved %p value %08lx\n", ptr->reg, ptr->val);
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}
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}
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/* s3c2410_pm_do_restore
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*
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* restore the system from the given list of saved registers
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*
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* Note, we do not use DBG() in here, as the system may not have
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* restore the UARTs state yet
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*/
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void s3c2410_pm_do_restore(struct sleep_save *ptr, int count)
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{
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for (; count > 0; count--, ptr++) {
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printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
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ptr->reg, ptr->val, __raw_readl(ptr->reg));
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__raw_writel(ptr->val, ptr->reg);
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}
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}
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/* s3c2410_pm_do_restore_core
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*
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* similar to s3c2410_pm_do_restore_core
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*
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* WARNING: Do not put any debug in here that may effect memory or use
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* peripherals, as things may be changing!
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*/
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static void s3c2410_pm_do_restore_core(struct sleep_save *ptr, int count)
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{
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for (; count > 0; count--, ptr++) {
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__raw_writel(ptr->val, ptr->reg);
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}
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}
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/* s3c2410_pm_show_resume_irqs
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*
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* print any IRQs asserted at resume time (ie, we woke from)
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*/
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static void s3c2410_pm_show_resume_irqs(int start, unsigned long which,
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unsigned long mask)
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{
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int i;
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which &= ~mask;
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for (i = 0; i <= 31; i++) {
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if ((which) & (1L<<i)) {
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DBG("IRQ %d asserted at resume\n", start+i);
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}
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}
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}
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/* s3c2410_pm_check_resume_pin
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*
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* check to see if the pin is configured correctly for sleep mode, and
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* make any necessary adjustments if it is not
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*/
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static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
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{
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unsigned long irqstate;
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unsigned long pinstate;
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int irq = s3c2410_gpio_getirq(pin);
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if (irqoffs < 4)
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irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
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else
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irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);
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pinstate = s3c2410_gpio_getcfg(pin);
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pinstate >>= S3C2410_GPIO_OFFSET(pin)*2;
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if (!irqstate) {
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if (pinstate == 0x02)
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DBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
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} else {
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if (pinstate == 0x02) {
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DBG("Disabling IRQ %d (pin %d)\n", irq, pin);
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s3c2410_gpio_cfgpin(pin, 0x00);
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}
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}
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}
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/* s3c2410_pm_configure_extint
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*
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* configure all external interrupt pins
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*/
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static void s3c2410_pm_configure_extint(void)
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{
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int pin;
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/* for each of the external interrupts (EINT0..EINT15) we
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* need to check wether it is an external interrupt source,
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* and then configure it as an input if it is not
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*/
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for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) {
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s3c2410_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
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}
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for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
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s3c2410_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
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}
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}
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#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
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/* s3c2410_pm_enter
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*
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* central control for sleep/resume process
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*/
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static int s3c2410_pm_enter(suspend_state_t state)
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{
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unsigned long regs_save[16];
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unsigned long tmp;
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/* ensure the debug is initialised (if enabled) */
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s3c2410_pm_debug_init();
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DBG("s3c2410_pm_enter(%d)\n", state);
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if (state != PM_SUSPEND_MEM) {
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printk(KERN_ERR PFX "error: only PM_SUSPEND_MEM supported\n");
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return -EINVAL;
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}
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/* check if we have anything to wake-up with... bad things seem
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* to happen if you suspend with no wakeup (system will often
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* require a full power-cycle)
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*/
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if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
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!any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
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printk(KERN_ERR PFX "No sources enabled for wake-up!\n");
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printk(KERN_ERR PFX "Aborting sleep\n");
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return -EINVAL;
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}
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/* prepare check area if configured */
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s3c2410_pm_check_prepare();
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/* store the physical address of the register recovery block */
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s3c2410_sleep_save_phys = virt_to_phys(regs_save);
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DBG("s3c2410_sleep_save_phys=0x%08lx\n", s3c2410_sleep_save_phys);
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/* ensure at least GESTATUS3 has the resume address */
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__raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2410_GSTATUS3);
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DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
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DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
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/* save all necessary core registers not covered by the drivers */
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s3c2410_pm_do_save(gpio_save, ARRAY_SIZE(gpio_save));
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s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
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s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save));
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s3c2410_pm_do_save(uart_save, ARRAY_SIZE(uart_save));
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/* set the irq configuration for wake */
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s3c2410_pm_configure_extint();
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DBG("sleep: irq wakeup masks: %08lx,%08lx\n",
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s3c_irqwake_intmask, s3c_irqwake_eintmask);
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__raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
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__raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
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/* ack any outstanding external interrupts before we go to sleep */
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__raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
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/* flush cache back to ram */
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arm920_flush_kern_cache_all();
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s3c2410_pm_check_store();
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/* send the cpu to sleep... */
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__raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */
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s3c2410_cpu_suspend(regs_save);
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/* restore the cpu state */
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cpu_init();
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/* unset the return-from-sleep flag, to ensure reset */
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tmp = __raw_readl(S3C2410_GSTATUS2);
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tmp &= S3C2410_GSTATUS2_OFFRESET;
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__raw_writel(tmp, S3C2410_GSTATUS2);
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/* restore the system state */
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|
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s3c2410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
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s3c2410_pm_do_restore(gpio_save, ARRAY_SIZE(gpio_save));
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s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
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s3c2410_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
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|
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s3c2410_pm_debug_init();
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/* check what irq (if any) restored the system */
|
|
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DBG("post sleep: IRQs 0x%08x, 0x%08x\n",
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__raw_readl(S3C2410_SRCPND),
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__raw_readl(S3C2410_EINTPEND));
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|
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s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
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s3c_irqwake_intmask);
|
|
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s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
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s3c_irqwake_eintmask);
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|
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DBG("post sleep, preparing to return\n");
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|
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s3c2410_pm_check_restore();
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|
|
|
/* ok, let's return from sleep */
|
|
|
|
DBG("S3C2410 PM Resume (post-restore)\n");
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Called after processes are frozen, but before we shut down devices.
|
|
*/
|
|
static int s3c2410_pm_prepare(suspend_state_t state)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Called after devices are re-setup, but before processes are thawed.
|
|
*/
|
|
static int s3c2410_pm_finish(suspend_state_t state)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
|
|
*/
|
|
static struct pm_ops s3c2410_pm_ops = {
|
|
.pm_disk_mode = PM_DISK_FIRMWARE,
|
|
.prepare = s3c2410_pm_prepare,
|
|
.enter = s3c2410_pm_enter,
|
|
.finish = s3c2410_pm_finish,
|
|
};
|
|
|
|
/* s3c2410_pm_init
|
|
*
|
|
* Attach the power management functions. This should be called
|
|
* from the board specific initialisation if the board supports
|
|
* it.
|
|
*/
|
|
|
|
int __init s3c2410_pm_init(void)
|
|
{
|
|
printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n");
|
|
|
|
pm_set_ops(&s3c2410_pm_ops);
|
|
return 0;
|
|
}
|