160 lines
5.3 KiB
C
160 lines
5.3 KiB
C
#ifndef __clkgen_defs_h
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#define __clkgen_defs_h
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/*
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* This file is autogenerated from
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* file: clkgen.r
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*
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* by ../../../tools/rdesc/bin/rdes2c -outfile clkgen_defs.h clkgen.r
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* Any changes here will be lost.
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*
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* -*- buffer-read-only: t -*-
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*/
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/* Main access macros */
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#ifndef REG_RD
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#define REG_RD( scope, inst, reg ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR
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#define REG_WR( scope, inst, reg, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_VECT
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#define REG_RD_VECT( scope, inst, reg, index ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_VECT
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#define REG_WR_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT
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#define REG_RD_INT( scope, inst, reg ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT
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#define REG_WR_INT( scope, inst, reg, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT_VECT
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#define REG_RD_INT_VECT( scope, inst, reg, index ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT_VECT
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#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_TYPE_CONV
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#define REG_TYPE_CONV( type, orgtype, val ) \
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( { union { orgtype o; type n; } r; r.o = val; r.n; } )
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#endif
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#ifndef reg_page_size
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#define reg_page_size 8192
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#endif
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#ifndef REG_ADDR
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#define REG_ADDR( scope, inst, reg ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_ADDR_VECT
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#define REG_ADDR_VECT( scope, inst, reg, index ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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/* C-code for register scope clkgen */
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/* Register r_bootsel, scope clkgen, type r */
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typedef struct {
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unsigned int boot_mode : 5;
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unsigned int intern_main_clk : 1;
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unsigned int extern_usb2_clk : 1;
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unsigned int dummy1 : 25;
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} reg_clkgen_r_bootsel;
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#define REG_RD_ADDR_clkgen_r_bootsel 0
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/* Register rw_clk_ctrl, scope clkgen, type rw */
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typedef struct {
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unsigned int pll : 1;
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unsigned int cpu : 1;
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unsigned int iop_usb : 1;
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unsigned int vin : 1;
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unsigned int sclr : 1;
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unsigned int h264 : 1;
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unsigned int ddr2 : 1;
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unsigned int vout_hist : 1;
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unsigned int eth : 1;
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unsigned int ccd_tg_200 : 1;
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unsigned int dma0_1_eth : 1;
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unsigned int ccd_tg_100 : 1;
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unsigned int jpeg : 1;
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unsigned int sser_ser_dma6_7 : 1;
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unsigned int strdma0_2_video : 1;
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unsigned int dma2_3_strcop : 1;
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unsigned int dma4_5_iop : 1;
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unsigned int dma9_11 : 1;
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unsigned int memarb_bar_ddr : 1;
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unsigned int sclr_h264 : 1;
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unsigned int dummy1 : 12;
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} reg_clkgen_rw_clk_ctrl;
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#define REG_RD_ADDR_clkgen_rw_clk_ctrl 4
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#define REG_WR_ADDR_clkgen_rw_clk_ctrl 4
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/* Constants */
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enum {
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regk_clkgen_eth1000_rx = 0x0000000c,
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regk_clkgen_eth1000_tx = 0x0000000e,
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regk_clkgen_eth100_rx = 0x0000001d,
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regk_clkgen_eth100_rx_half = 0x0000001c,
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regk_clkgen_eth100_tx = 0x0000001f,
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regk_clkgen_eth100_tx_half = 0x0000001e,
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regk_clkgen_nand_3_2 = 0x00000000,
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regk_clkgen_nand_3_2_0x30 = 0x00000002,
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regk_clkgen_nand_3_2_0x30_pll = 0x00000012,
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regk_clkgen_nand_3_2_pll = 0x00000010,
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regk_clkgen_nand_3_3 = 0x00000001,
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regk_clkgen_nand_3_3_0x30 = 0x00000003,
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regk_clkgen_nand_3_3_0x30_pll = 0x00000013,
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regk_clkgen_nand_3_3_pll = 0x00000011,
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regk_clkgen_nand_4_2 = 0x00000004,
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regk_clkgen_nand_4_2_0x30 = 0x00000006,
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regk_clkgen_nand_4_2_0x30_pll = 0x00000016,
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regk_clkgen_nand_4_2_pll = 0x00000014,
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regk_clkgen_nand_4_3 = 0x00000005,
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regk_clkgen_nand_4_3_0x30 = 0x00000007,
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regk_clkgen_nand_4_3_0x30_pll = 0x00000017,
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regk_clkgen_nand_4_3_pll = 0x00000015,
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regk_clkgen_nand_5_2 = 0x00000008,
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regk_clkgen_nand_5_2_0x30 = 0x0000000a,
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regk_clkgen_nand_5_2_0x30_pll = 0x0000001a,
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regk_clkgen_nand_5_2_pll = 0x00000018,
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regk_clkgen_nand_5_3 = 0x00000009,
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regk_clkgen_nand_5_3_0x30 = 0x0000000b,
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regk_clkgen_nand_5_3_0x30_pll = 0x0000001b,
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regk_clkgen_nand_5_3_pll = 0x00000019,
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regk_clkgen_no = 0x00000000,
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regk_clkgen_rw_clk_ctrl_default = 0x00000002,
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regk_clkgen_ser = 0x0000000d,
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regk_clkgen_ser_pll = 0x0000000f,
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regk_clkgen_yes = 0x00000001
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};
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#endif /* __clkgen_defs_h */
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