75 lines
1.9 KiB
C
75 lines
1.9 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2002-2004 Silicon Graphics, Inc. All Rights Reserved.
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*/
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#ifndef _ASM_IA64_SN_RW_MMR_H
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#define _ASM_IA64_SN_RW_MMR_H
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/*
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* This file contains macros used to access MMR registers via
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* uncached physical addresses.
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* pio_phys_read_mmr - read an MMR
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* pio_phys_write_mmr - write an MMR
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* pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0
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* Second MMR will be skipped if address is NULL
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*
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* Addresses passed to these routines should be uncached physical addresses
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* ie., 0x80000....
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*/
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extern inline long
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pio_phys_read_mmr(volatile long *mmr)
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{
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long val;
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asm volatile
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("mov r2=psr;;"
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"rsm psr.i | psr.dt;;"
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"srlz.i;;"
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"ld8.acq %0=[%1];;"
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"mov psr.l=r2;;"
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"srlz.i;;"
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: "=r"(val)
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: "r"(mmr)
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: "r2");
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return val;
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}
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extern inline void
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pio_phys_write_mmr(volatile long *mmr, long val)
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{
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asm volatile
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("mov r2=psr;;"
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"rsm psr.i | psr.dt;;"
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"srlz.i;;"
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"st8.rel [%0]=%1;;"
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"mov psr.l=r2;;"
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"srlz.i;;"
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:: "r"(mmr), "r"(val)
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: "r2", "memory");
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}
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extern inline void
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pio_atomic_phys_write_mmrs(volatile long *mmr1, long val1, volatile long *mmr2, long val2)
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{
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asm volatile
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("mov r2=psr;;"
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"rsm psr.i | psr.dt | psr.ic;;"
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"cmp.ne p9,p0=%2,r0;"
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"srlz.i;;"
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"st8.rel [%0]=%1;"
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"(p9) st8.rel [%2]=%3;;"
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"mov psr.l=r2;;"
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"srlz.i;;"
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:: "r"(mmr1), "r"(val1), "r"(mmr2), "r"(val2)
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: "p9", "r2", "memory");
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}
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#endif /* _ASM_IA64_SN_RW_MMR_H */
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