224 lines
5.8 KiB
C
224 lines
5.8 KiB
C
/*
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* File: include/asm-blackfin/mach-bf561/bf561.h
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* Based on:
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* Author:
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*
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* Created:
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* Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
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*
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* Modified:
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* Copyright 2004-2006 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __MACH_BF561_H__
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#define __MACH_BF561_H__
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#define SUPPORTED_REVID 0x3
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#define OFFSET_(x) ((x) & 0x0000FFFF)
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/*some misc defines*/
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#define IMASK_IVG15 0x8000
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#define IMASK_IVG14 0x4000
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#define IMASK_IVG13 0x2000
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#define IMASK_IVG12 0x1000
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#define IMASK_IVG11 0x0800
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#define IMASK_IVG10 0x0400
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#define IMASK_IVG9 0x0200
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#define IMASK_IVG8 0x0100
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#define IMASK_IVG7 0x0080
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#define IMASK_IVGTMR 0x0040
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#define IMASK_IVGHW 0x0020
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/***************************
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* Blackfin Cache setup
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*/
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#define BFIN_ISUBBANKS 4
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#define BFIN_IWAYS 4
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#define BFIN_ILINES 32
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#define BFIN_DSUBBANKS 4
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#define BFIN_DWAYS 2
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#define BFIN_DLINES 64
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#define WAY0_L 0x1
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#define WAY1_L 0x2
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#define WAY01_L 0x3
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#define WAY2_L 0x4
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#define WAY02_L 0x5
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#define WAY12_L 0x6
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#define WAY012_L 0x7
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#define WAY3_L 0x8
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#define WAY03_L 0x9
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#define WAY13_L 0xA
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#define WAY013_L 0xB
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#define WAY32_L 0xC
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#define WAY320_L 0xD
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#define WAY321_L 0xE
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#define WAYALL_L 0xF
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#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
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/* IAR0 BIT FIELDS */
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#define PLL_WAKEUP_BIT 0xFFFFFFFF
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#define DMA1_ERROR_BIT 0xFFFFFF0F
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#define DMA2_ERROR_BIT 0xFFFFF0FF
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#define IMDMA_ERROR_BIT 0xFFFF0FFF
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#define PPI1_ERROR_BIT 0xFFF0FFFF
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#define PPI2_ERROR_BIT 0xFF0FFFFF
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#define SPORT0_ERROR_BIT 0xF0FFFFFF
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#define SPORT1_ERROR_BIT 0x0FFFFFFF
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/* IAR1 BIT FIELDS */
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#define SPI_ERROR_BIT 0xFFFFFFFF
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#define UART_ERROR_BIT 0xFFFFFF0F
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#define RESERVED_ERROR_BIT 0xFFFFF0FF
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#define DMA1_0_BIT 0xFFFF0FFF
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#define DMA1_1_BIT 0xFFF0FFFF
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#define DMA1_2_BIT 0xFF0FFFFF
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#define DMA1_3_BIT 0xF0FFFFFF
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#define DMA1_4_BIT 0x0FFFFFFF
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/* IAR2 BIT FIELDS */
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#define DMA1_5_BIT 0xFFFFFFFF
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#define DMA1_6_BIT 0xFFFFFF0F
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#define DMA1_7_BIT 0xFFFFF0FF
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#define DMA1_8_BIT 0xFFFF0FFF
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#define DMA1_9_BIT 0xFFF0FFFF
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#define DMA1_10_BIT 0xFF0FFFFF
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#define DMA1_11_BIT 0xF0FFFFFF
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#define DMA2_0_BIT 0x0FFFFFFF
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/* IAR3 BIT FIELDS */
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#define DMA2_1_BIT 0xFFFFFFFF
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#define DMA2_2_BIT 0xFFFFFF0F
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#define DMA2_3_BIT 0xFFFFF0FF
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#define DMA2_4_BIT 0xFFFF0FFF
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#define DMA2_5_BIT 0xFFF0FFFF
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#define DMA2_6_BIT 0xFF0FFFFF
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#define DMA2_7_BIT 0xF0FFFFFF
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#define DMA2_8_BIT 0x0FFFFFFF
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/* IAR4 BIT FIELDS */
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#define DMA2_9_BIT 0xFFFFFFFF
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#define DMA2_10_BIT 0xFFFFFF0F
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#define DMA2_11_BIT 0xFFFFF0FF
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#define TIMER0_BIT 0xFFFF0FFF
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#define TIMER1_BIT 0xFFF0FFFF
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#define TIMER2_BIT 0xFF0FFFFF
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#define TIMER3_BIT 0xF0FFFFFF
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#define TIMER4_BIT 0x0FFFFFFF
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/* IAR5 BIT FIELDS */
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#define TIMER5_BIT 0xFFFFFFFF
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#define TIMER6_BIT 0xFFFFFF0F
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#define TIMER7_BIT 0xFFFFF0FF
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#define TIMER8_BIT 0xFFFF0FFF
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#define TIMER9_BIT 0xFFF0FFFF
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#define TIMER10_BIT 0xFF0FFFFF
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#define TIMER11_BIT 0xF0FFFFFF
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#define PROG0_INTA_BIT 0x0FFFFFFF
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/* IAR6 BIT FIELDS */
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#define PROG0_INTB_BIT 0xFFFFFFFF
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#define PROG1_INTA_BIT 0xFFFFFF0F
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#define PROG1_INTB_BIT 0xFFFFF0FF
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#define PROG2_INTA_BIT 0xFFFF0FFF
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#define PROG2_INTB_BIT 0xFFF0FFFF
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#define DMA1_WRRD0_BIT 0xFF0FFFFF
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#define DMA1_WRRD1_BIT 0xF0FFFFFF
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#define DMA2_WRRD0_BIT 0x0FFFFFFF
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/* IAR7 BIT FIELDS */
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#define DMA2_WRRD1_BIT 0xFFFFFFFF
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#define IMDMA_WRRD0_BIT 0xFFFFFF0F
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#define IMDMA_WRRD1_BIT 0xFFFFF0FF
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#define WATCH_BIT 0xFFFF0FFF
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#define RESERVED_1_BIT 0xFFF0FFFF
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#define RESERVED_2_BIT 0xFF0FFFFF
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#define SUPPLE_0_BIT 0xF0FFFFFF
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#define SUPPLE_1_BIT 0x0FFFFFFF
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/* Miscellaneous Values */
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/****************************** EBIU Settings ********************************/
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#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
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#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
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#if defined(CONFIG_C_AMBEN_ALL)
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#define V_AMBEN AMBEN_ALL
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#elif defined(CONFIG_C_AMBEN)
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#define V_AMBEN 0x0
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#elif defined(CONFIG_C_AMBEN_B0)
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#define V_AMBEN AMBEN_B0
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#elif defined(CONFIG_C_AMBEN_B0_B1)
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#define V_AMBEN AMBEN_B0_B1
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#elif defined(CONFIG_C_AMBEN_B0_B1_B2)
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#define V_AMBEN AMBEN_B0_B1_B2
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#endif
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#ifdef CONFIG_C_AMCKEN
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#define V_AMCKEN AMCKEN
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#else
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#define V_AMCKEN 0x0
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#endif
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#ifdef CONFIG_C_B0PEN
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#define V_B0PEN 0x10
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#else
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#define V_B0PEN 0x00
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#endif
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#ifdef CONFIG_C_B1PEN
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#define V_B1PEN 0x20
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#else
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#define V_B1PEN 0x00
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#endif
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#ifdef CONFIG_C_B2PEN
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#define V_B2PEN 0x40
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#else
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#define V_B2PEN 0x00
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#endif
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#ifdef CONFIG_C_B3PEN
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#define V_B3PEN 0x80
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#else
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#define V_B3PEN 0x00
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#endif
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#ifdef CONFIG_C_CDPRIO
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#define V_CDPRIO 0x100
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#else
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#define V_CDPRIO 0x0
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#endif
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#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002)
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#ifdef CONFIG_BF561
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#define CPU "BF561"
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#define CPUID 0x027bb000
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#endif
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#ifndef CPU
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#define CPU "UNKNOWN"
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#define CPUID 0x0
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#endif
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#endif /* __MACH_BF561_H__ */
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