282 lines
6.5 KiB
C
282 lines
6.5 KiB
C
/*
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* Copyright (C) 2009 Extreme Engineering Solutions, Inc.
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*
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* X-ES board-specific functionality
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*
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* Based on mpc85xx_ds code from Freescale Semiconductor, Inc.
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*
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* Author: Nate Case <ncase@xes-inc.com>
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/interrupt.h>
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#include <linux/of_platform.h>
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#include <asm/system.h>
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#include <asm/time.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <mm/mmu_decl.h>
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#include <asm/prom.h>
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#include <asm/udbg.h>
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#include <asm/mpic.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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/* A few bit definitions needed for fixups on some boards */
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#define MPC85xx_L2CTL_L2E 0x80000000 /* L2 enable */
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#define MPC85xx_L2CTL_L2I 0x40000000 /* L2 flash invalidate */
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#define MPC85xx_L2CTL_L2SIZ_MASK 0x30000000 /* L2 SRAM size (R/O) */
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void __init xes_mpc85xx_pic_init(void)
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{
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struct mpic *mpic;
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struct resource r;
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struct device_node *np;
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np = of_find_node_by_type(NULL, "open-pic");
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if (np == NULL) {
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printk(KERN_ERR "Could not find open-pic node\n");
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return;
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}
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if (of_address_to_resource(np, 0, &r)) {
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printk(KERN_ERR "Failed to map mpic register space\n");
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of_node_put(np);
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return;
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}
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mpic = mpic_alloc(np, r.start,
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MPIC_PRIMARY | MPIC_WANTS_RESET |
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MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
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0, 256, " OpenPIC ");
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BUG_ON(mpic == NULL);
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of_node_put(np);
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mpic_init(mpic);
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}
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static void xes_mpc85xx_configure_l2(void __iomem *l2_base)
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{
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volatile uint32_t ctl, tmp;
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asm volatile("msync; isync");
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tmp = in_be32(l2_base);
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/*
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* xMon may have enabled part of L2 as SRAM, so we need to set it
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* up for all cache mode just to be safe.
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*/
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printk(KERN_INFO "xes_mpc85xx: Enabling L2 as cache\n");
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ctl = MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2I;
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if (machine_is_compatible("MPC8540") ||
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machine_is_compatible("MPC8560"))
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/*
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* Assume L2 SRAM is used fully for cache, so set
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* L2BLKSZ (bits 4:5) to match L2SIZ (bits 2:3).
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*/
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ctl |= (tmp & MPC85xx_L2CTL_L2SIZ_MASK) >> 2;
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asm volatile("msync; isync");
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out_be32(l2_base, ctl);
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asm volatile("msync; isync");
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}
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static void xes_mpc85xx_fixups(void)
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{
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struct device_node *np;
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int err;
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/*
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* Legacy xMon firmware on some X-ES boards does not enable L2
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* as cache. We must ensure that they get enabled here.
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*/
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for_each_node_by_name(np, "l2-cache-controller") {
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struct resource r[2];
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void __iomem *l2_base;
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/* Only MPC8548, MPC8540, and MPC8560 boards are affected */
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if (!of_device_is_compatible(np,
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"fsl,mpc8548-l2-cache-controller") &&
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!of_device_is_compatible(np,
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"fsl,mpc8540-l2-cache-controller") &&
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!of_device_is_compatible(np,
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"fsl,mpc8560-l2-cache-controller"))
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continue;
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err = of_address_to_resource(np, 0, &r[0]);
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if (err) {
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printk(KERN_WARNING "xes_mpc85xx: Could not get "
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"resource for device tree node '%s'",
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np->full_name);
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continue;
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}
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l2_base = ioremap(r[0].start, r[0].end - r[0].start + 1);
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xes_mpc85xx_configure_l2(l2_base);
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}
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}
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#ifdef CONFIG_PCI
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static int primary_phb_addr;
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#endif
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/*
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* Setup the architecture
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*/
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#ifdef CONFIG_SMP
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extern void __init mpc85xx_smp_init(void);
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#endif
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static void __init xes_mpc85xx_setup_arch(void)
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{
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#ifdef CONFIG_PCI
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struct device_node *np;
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#endif
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struct device_node *root;
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const char *model = "Unknown";
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root = of_find_node_by_path("/");
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if (root == NULL)
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return;
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model = of_get_property(root, "model", NULL);
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printk(KERN_INFO "X-ES MPC85xx-based single-board computer: %s\n",
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model + strlen("xes,"));
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xes_mpc85xx_fixups();
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#ifdef CONFIG_PCI
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for_each_node_by_type(np, "pci") {
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if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
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of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
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struct resource rsrc;
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of_address_to_resource(np, 0, &rsrc);
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if ((rsrc.start & 0xfffff) == primary_phb_addr)
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fsl_add_bridge(np, 1);
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else
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fsl_add_bridge(np, 0);
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}
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}
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#endif
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#ifdef CONFIG_SMP
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mpc85xx_smp_init();
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#endif
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}
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static struct of_device_id __initdata xes_mpc85xx_ids[] = {
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{ .type = "soc", },
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{ .compatible = "soc", },
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{ .compatible = "simple-bus", },
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{ .compatible = "gianfar", },
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{},
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};
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static int __init xes_mpc85xx_publish_devices(void)
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{
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return of_platform_bus_probe(NULL, xes_mpc85xx_ids, NULL);
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}
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machine_device_initcall(xes_mpc8572, xes_mpc85xx_publish_devices);
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machine_device_initcall(xes_mpc8548, xes_mpc85xx_publish_devices);
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machine_device_initcall(xes_mpc8540, xes_mpc85xx_publish_devices);
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init xes_mpc8572_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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if (of_flat_dt_is_compatible(root, "xes,MPC8572")) {
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#ifdef CONFIG_PCI
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primary_phb_addr = 0x8000;
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#endif
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return 1;
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} else {
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return 0;
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}
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}
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static int __init xes_mpc8548_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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if (of_flat_dt_is_compatible(root, "xes,MPC8548")) {
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#ifdef CONFIG_PCI
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primary_phb_addr = 0xb000;
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#endif
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return 1;
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} else {
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return 0;
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}
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}
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static int __init xes_mpc8540_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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if (of_flat_dt_is_compatible(root, "xes,MPC8540")) {
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#ifdef CONFIG_PCI
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primary_phb_addr = 0xb000;
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#endif
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return 1;
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} else {
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return 0;
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}
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}
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define_machine(xes_mpc8572) {
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.name = "X-ES MPC8572",
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.probe = xes_mpc8572_probe,
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.setup_arch = xes_mpc85xx_setup_arch,
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.init_IRQ = xes_mpc85xx_pic_init,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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define_machine(xes_mpc8548) {
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.name = "X-ES MPC8548",
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.probe = xes_mpc8548_probe,
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.setup_arch = xes_mpc85xx_setup_arch,
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.init_IRQ = xes_mpc85xx_pic_init,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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define_machine(xes_mpc8540) {
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.name = "X-ES MPC8540",
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.probe = xes_mpc8540_probe,
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.setup_arch = xes_mpc85xx_setup_arch,
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.init_IRQ = xes_mpc85xx_pic_init,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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