159 lines
3.9 KiB
C
159 lines
3.9 KiB
C
/*
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* arch/mips/emma2rh/markeins/irq_markeins.c
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* This file defines the irq handler for Mark-eins.
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*
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* Copyright (C) NEC Electronics Corporation 2004-2006
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*
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* This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c
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*
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* Copyright 2001 MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <asm/debug.h>
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#include <asm/emma2rh/emma2rh.h>
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static int emma2rh_sw_irq_base = -1;
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static int emma2rh_gpio_irq_base = -1;
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void ll_emma2rh_sw_irq_enable(int reg);
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void ll_emma2rh_sw_irq_disable(int reg);
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void ll_emma2rh_gpio_irq_enable(int reg);
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void ll_emma2rh_gpio_irq_disable(int reg);
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static void emma2rh_sw_irq_enable(unsigned int irq)
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{
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ll_emma2rh_sw_irq_enable(irq - emma2rh_sw_irq_base);
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}
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static void emma2rh_sw_irq_disable(unsigned int irq)
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{
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ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
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}
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struct irq_chip emma2rh_sw_irq_controller = {
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.typename = "emma2rh_sw_irq",
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.ack = emma2rh_sw_irq_disable,
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.mask = emma2rh_sw_irq_disable,
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.mask_ack = emma2rh_sw_irq_disable,
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.unmask = emma2rh_sw_irq_enable,
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};
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void emma2rh_sw_irq_init(u32 irq_base)
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{
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u32 i;
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for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++)
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set_irq_chip_and_handler(i, &emma2rh_sw_irq_controller,
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handle_level_irq);
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emma2rh_sw_irq_base = irq_base;
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}
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void ll_emma2rh_sw_irq_enable(int irq)
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{
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u32 reg;
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db_assert(irq >= 0);
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db_assert(irq < NUM_EMMA2RH_IRQ_SW);
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reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
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reg |= 1 << irq;
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emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
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}
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void ll_emma2rh_sw_irq_disable(int irq)
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{
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u32 reg;
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db_assert(irq >= 0);
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db_assert(irq < 32);
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reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
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reg &= ~(1 << irq);
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emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
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}
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static void emma2rh_gpio_irq_enable(unsigned int irq)
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{
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ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base);
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}
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static void emma2rh_gpio_irq_disable(unsigned int irq)
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{
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ll_emma2rh_gpio_irq_disable(irq - emma2rh_gpio_irq_base);
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}
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static void emma2rh_gpio_irq_ack(unsigned int irq)
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{
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irq -= emma2rh_gpio_irq_base;
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emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
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ll_emma2rh_gpio_irq_disable(irq);
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}
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static void emma2rh_gpio_irq_end(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base);
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}
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struct irq_chip emma2rh_gpio_irq_controller = {
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.typename = "emma2rh_gpio_irq",
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.ack = emma2rh_gpio_irq_ack,
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.mask = emma2rh_gpio_irq_disable,
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.mask_ack = emma2rh_gpio_irq_ack,
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.unmask = emma2rh_gpio_irq_enable,
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.end = emma2rh_gpio_irq_end,
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};
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void emma2rh_gpio_irq_init(u32 irq_base)
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{
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u32 i;
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for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_GPIO; i++)
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set_irq_chip(i, &emma2rh_gpio_irq_controller);
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emma2rh_gpio_irq_base = irq_base;
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}
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void ll_emma2rh_gpio_irq_enable(int irq)
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{
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u32 reg;
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db_assert(irq >= 0);
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db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
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reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
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reg |= 1 << irq;
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emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
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}
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void ll_emma2rh_gpio_irq_disable(int irq)
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{
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u32 reg;
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db_assert(irq >= 0);
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db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
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reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
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reg &= ~(1 << irq);
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emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
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}
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