Josh Boyer fbcc4bacee ibm_newemac: MAL support for PowerPC 405EZ ... The PowerPC 405EZ SoC has some differences in the interrupt layout and handling for the MAL. The SERR, TXDE, and RXDE interrupts are OR'd into a single interrupt. Also, due to the possibility for interrupt coalescing, the TXEOB and RXEOB interrupts require an interrupt bit to be cleared in the ICINTSTAT SDR. This sets the proper MAL feature bits for 405EZ boards, and adds a common shared handler for SERR, TXDE, and RXDE. The defines for the ICINTSTAT DCR are added to the proper header file as well. This has been adapted from code originally written by Stefan Roese. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>		2008-09-30 09:23:15 -04:00
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Kconfig	ibm_newemac: Introduce mal_has_feature	2008-09-30 09:23:04 -04:00
Makefile	…
core.c	ibm_newemac: Allow the "no flow control" EMAC feature to work	2008-09-30 09:22:45 -04:00
core.h	ibm_newemac: Allow the "no flow control" EMAC feature to work	2008-09-30 09:22:45 -04:00
debug.c	…
debug.h	…
emac.h	…
mal.c	ibm_newemac: MAL support for PowerPC 405EZ	2008-09-30 09:23:15 -04:00
mal.h	ibm_newemac: Introduce mal_has_feature	2008-09-30 09:23:04 -04:00
phy.c	…
phy.h	…
rgmii.c	…
rgmii.h	…
tah.c	…
tah.h	…
zmii.c	…
zmii.h	…