432 lines
13 KiB
C
432 lines
13 KiB
C
/*
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* isp.h
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*
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* TI OMAP3 ISP - Core
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*
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* Copyright (C) 2009-2010 Nokia Corporation
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* Copyright (C) 2009 Texas Instruments, Inc.
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*
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* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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* Sakari Ailus <sakari.ailus@iki.fi>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*/
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#ifndef OMAP3_ISP_CORE_H
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#define OMAP3_ISP_CORE_H
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#include <media/v4l2-device.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/wait.h>
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#include <plat/iommu.h>
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#include <plat/iovmm.h>
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#include "ispstat.h"
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#include "ispccdc.h"
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#include "ispreg.h"
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#include "ispresizer.h"
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#include "isppreview.h"
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#include "ispcsiphy.h"
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#include "ispcsi2.h"
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#include "ispccp2.h"
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#define IOMMU_FLAG (IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_8)
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#define ISP_TOK_TERM 0xFFFFFFFF /*
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* terminating token for ISP
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* modules reg list
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*/
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#define to_isp_device(ptr_module) \
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container_of(ptr_module, struct isp_device, isp_##ptr_module)
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#define to_device(ptr_module) \
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(to_isp_device(ptr_module)->dev)
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enum isp_mem_resources {
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OMAP3_ISP_IOMEM_MAIN,
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OMAP3_ISP_IOMEM_CCP2,
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OMAP3_ISP_IOMEM_CCDC,
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OMAP3_ISP_IOMEM_HIST,
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OMAP3_ISP_IOMEM_H3A,
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OMAP3_ISP_IOMEM_PREV,
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OMAP3_ISP_IOMEM_RESZ,
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OMAP3_ISP_IOMEM_SBL,
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OMAP3_ISP_IOMEM_CSI2A_REGS1,
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OMAP3_ISP_IOMEM_CSIPHY2,
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OMAP3_ISP_IOMEM_CSI2A_REGS2,
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OMAP3_ISP_IOMEM_CSI2C_REGS1,
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OMAP3_ISP_IOMEM_CSIPHY1,
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OMAP3_ISP_IOMEM_CSI2C_REGS2,
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OMAP3_ISP_IOMEM_LAST
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};
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enum isp_sbl_resource {
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OMAP3_ISP_SBL_CSI1_READ = 0x1,
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OMAP3_ISP_SBL_CSI1_WRITE = 0x2,
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OMAP3_ISP_SBL_CSI2A_WRITE = 0x4,
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OMAP3_ISP_SBL_CSI2C_WRITE = 0x8,
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OMAP3_ISP_SBL_CCDC_LSC_READ = 0x10,
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OMAP3_ISP_SBL_CCDC_WRITE = 0x20,
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OMAP3_ISP_SBL_PREVIEW_READ = 0x40,
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OMAP3_ISP_SBL_PREVIEW_WRITE = 0x80,
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OMAP3_ISP_SBL_RESIZER_READ = 0x100,
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OMAP3_ISP_SBL_RESIZER_WRITE = 0x200,
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};
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enum isp_subclk_resource {
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OMAP3_ISP_SUBCLK_CCDC = (1 << 0),
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OMAP3_ISP_SUBCLK_H3A = (1 << 1),
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OMAP3_ISP_SUBCLK_HIST = (1 << 2),
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OMAP3_ISP_SUBCLK_PREVIEW = (1 << 3),
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OMAP3_ISP_SUBCLK_RESIZER = (1 << 4),
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};
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enum isp_interface_type {
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ISP_INTERFACE_PARALLEL,
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ISP_INTERFACE_CSI2A_PHY2,
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ISP_INTERFACE_CCP2B_PHY1,
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ISP_INTERFACE_CCP2B_PHY2,
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ISP_INTERFACE_CSI2C_PHY1,
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};
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/* ISP: OMAP 34xx ES 1.0 */
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#define ISP_REVISION_1_0 0x10
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/* ISP2: OMAP 34xx ES 2.0, 2.1 and 3.0 */
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#define ISP_REVISION_2_0 0x20
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/* ISP2P: OMAP 36xx */
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#define ISP_REVISION_15_0 0xF0
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/*
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* struct isp_res_mapping - Map ISP io resources to ISP revision.
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* @isp_rev: ISP_REVISION_x_x
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* @map: bitmap for enum isp_mem_resources
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*/
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struct isp_res_mapping {
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u32 isp_rev;
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u32 map;
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};
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/*
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* struct isp_reg - Structure for ISP register values.
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* @reg: 32-bit Register address.
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* @val: 32-bit Register value.
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*/
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struct isp_reg {
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enum isp_mem_resources mmio_range;
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u32 reg;
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u32 val;
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};
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/**
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* struct isp_parallel_platform_data - Parallel interface platform data
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* @data_lane_shift: Data lane shifter
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* 0 - CAMEXT[13:0] -> CAM[13:0]
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* 1 - CAMEXT[13:2] -> CAM[11:0]
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* 2 - CAMEXT[13:4] -> CAM[9:0]
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* 3 - CAMEXT[13:6] -> CAM[7:0]
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* @clk_pol: Pixel clock polarity
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* 0 - Non Inverted, 1 - Inverted
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* @bridge: CCDC Bridge input control
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* ISPCTRL_PAR_BRIDGE_DISABLE - Disable
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* ISPCTRL_PAR_BRIDGE_LENDIAN - Little endian
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* ISPCTRL_PAR_BRIDGE_BENDIAN - Big endian
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*/
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struct isp_parallel_platform_data {
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unsigned int data_lane_shift:2;
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unsigned int clk_pol:1;
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unsigned int bridge:4;
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};
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/**
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* struct isp_ccp2_platform_data - CCP2 interface platform data
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* @strobe_clk_pol: Strobe/clock polarity
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* 0 - Non Inverted, 1 - Inverted
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* @crc: Enable the cyclic redundancy check
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* @ccp2_mode: Enable CCP2 compatibility mode
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* 0 - MIPI-CSI1 mode, 1 - CCP2 mode
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* @phy_layer: Physical layer selection
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* ISPCCP2_CTRL_PHY_SEL_CLOCK - Data/clock physical layer
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* ISPCCP2_CTRL_PHY_SEL_STROBE - Data/strobe physical layer
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* @vpclk_div: Video port output clock control
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*/
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struct isp_ccp2_platform_data {
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unsigned int strobe_clk_pol:1;
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unsigned int crc:1;
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unsigned int ccp2_mode:1;
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unsigned int phy_layer:1;
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unsigned int vpclk_div:2;
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};
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/**
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* struct isp_csi2_platform_data - CSI2 interface platform data
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* @crc: Enable the cyclic redundancy check
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* @vpclk_div: Video port output clock control
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*/
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struct isp_csi2_platform_data {
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unsigned crc:1;
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unsigned vpclk_div:2;
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};
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struct isp_subdev_i2c_board_info {
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struct i2c_board_info *board_info;
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int i2c_adapter_id;
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};
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struct isp_v4l2_subdevs_group {
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struct isp_subdev_i2c_board_info *subdevs;
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enum isp_interface_type interface;
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union {
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struct isp_parallel_platform_data parallel;
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struct isp_ccp2_platform_data ccp2;
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struct isp_csi2_platform_data csi2;
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} bus; /* gcc < 4.6.0 chokes on anonymous union initializers */
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};
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struct isp_platform_data {
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struct isp_v4l2_subdevs_group *subdevs;
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void (*set_constraints)(struct isp_device *isp, bool enable);
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};
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struct isp_platform_callback {
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u32 (*set_xclk)(struct isp_device *isp, u32 xclk, u8 xclksel);
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int (*csiphy_config)(struct isp_csiphy *phy,
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struct isp_csiphy_dphy_cfg *dphy,
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struct isp_csiphy_lanes_cfg *lanes);
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void (*set_pixel_clock)(struct isp_device *isp, unsigned int pixelclk);
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};
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/*
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* struct isp_device - ISP device structure.
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* @dev: Device pointer specific to the OMAP3 ISP.
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* @revision: Stores current ISP module revision.
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* @irq_num: Currently used IRQ number.
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* @mmio_base: Array with kernel base addresses for ioremapped ISP register
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* regions.
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* @mmio_base_phys: Array with physical L4 bus addresses for ISP register
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* regions.
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* @mmio_size: Array with ISP register regions size in bytes.
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* @raw_dmamask: Raw DMA mask
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* @stat_lock: Spinlock for handling statistics
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* @isp_mutex: Mutex for serializing requests to ISP.
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* @has_context: Context has been saved at least once and can be restored.
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* @ref_count: Reference count for handling multiple ISP requests.
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* @cam_ick: Pointer to camera interface clock structure.
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* @cam_mclk: Pointer to camera functional clock structure.
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* @dpll4_m5_ck: Pointer to DPLL4 M5 clock structure.
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* @csi2_fck: Pointer to camera CSI2 complexIO clock structure.
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* @l3_ick: Pointer to OMAP3 L3 bus interface clock.
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* @irq: Currently attached ISP ISR callbacks information structure.
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* @isp_af: Pointer to current settings for ISP AutoFocus SCM.
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* @isp_hist: Pointer to current settings for ISP Histogram SCM.
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* @isp_h3a: Pointer to current settings for ISP Auto Exposure and
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* White Balance SCM.
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* @isp_res: Pointer to current settings for ISP Resizer.
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* @isp_prev: Pointer to current settings for ISP Preview.
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* @isp_ccdc: Pointer to current settings for ISP CCDC.
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* @iommu: Pointer to requested IOMMU instance for ISP.
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* @platform_cb: ISP driver callback function pointers for platform code
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*
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* This structure is used to store the OMAP ISP Information.
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*/
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struct isp_device {
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struct v4l2_device v4l2_dev;
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struct media_device media_dev;
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struct device *dev;
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u32 revision;
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/* platform HW resources */
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struct isp_platform_data *pdata;
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unsigned int irq_num;
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void __iomem *mmio_base[OMAP3_ISP_IOMEM_LAST];
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unsigned long mmio_base_phys[OMAP3_ISP_IOMEM_LAST];
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resource_size_t mmio_size[OMAP3_ISP_IOMEM_LAST];
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u64 raw_dmamask;
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/* ISP Obj */
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spinlock_t stat_lock; /* common lock for statistic drivers */
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struct mutex isp_mutex; /* For handling ref_count field */
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bool needs_reset;
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int has_context;
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int ref_count;
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unsigned int autoidle;
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u32 xclk_divisor[2]; /* Two clocks, a and b. */
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#define ISP_CLK_CAM_ICK 0
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#define ISP_CLK_CAM_MCLK 1
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#define ISP_CLK_DPLL4_M5_CK 2
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#define ISP_CLK_CSI2_FCK 3
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#define ISP_CLK_L3_ICK 4
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struct clk *clock[5];
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/* ISP modules */
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struct ispstat isp_af;
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struct ispstat isp_aewb;
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struct ispstat isp_hist;
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struct isp_res_device isp_res;
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struct isp_prev_device isp_prev;
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struct isp_ccdc_device isp_ccdc;
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struct isp_csi2_device isp_csi2a;
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struct isp_csi2_device isp_csi2c;
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struct isp_ccp2_device isp_ccp2;
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struct isp_csiphy isp_csiphy1;
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struct isp_csiphy isp_csiphy2;
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unsigned int sbl_resources;
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unsigned int subclk_resources;
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struct iommu *iommu;
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struct isp_platform_callback platform_cb;
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};
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#define v4l2_dev_to_isp_device(dev) \
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container_of(dev, struct isp_device, v4l2_dev)
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void omap3isp_hist_dma_done(struct isp_device *isp);
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void omap3isp_flush(struct isp_device *isp);
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int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
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atomic_t *stopping);
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int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
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atomic_t *stopping);
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int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
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enum isp_pipeline_stream_state state);
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void omap3isp_configure_bridge(struct isp_device *isp,
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enum ccdc_input_entity input,
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const struct isp_parallel_platform_data *pdata,
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unsigned int shift);
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#define ISP_XCLK_NONE 0
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#define ISP_XCLK_A 1
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#define ISP_XCLK_B 2
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struct isp_device *omap3isp_get(struct isp_device *isp);
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void omap3isp_put(struct isp_device *isp);
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void omap3isp_print_status(struct isp_device *isp);
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void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res);
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void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res);
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void omap3isp_subclk_enable(struct isp_device *isp,
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enum isp_subclk_resource res);
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void omap3isp_subclk_disable(struct isp_device *isp,
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enum isp_subclk_resource res);
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int omap3isp_pipeline_pm_use(struct media_entity *entity, int use);
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int omap3isp_register_entities(struct platform_device *pdev,
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struct v4l2_device *v4l2_dev);
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void omap3isp_unregister_entities(struct platform_device *pdev);
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/*
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* isp_reg_readl - Read value of an OMAP3 ISP register
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* @dev: Device pointer specific to the OMAP3 ISP.
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* @isp_mmio_range: Range to which the register offset refers to.
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* @reg_offset: Register offset to read from.
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*
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* Returns an unsigned 32 bit value with the required register contents.
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*/
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static inline
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u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range,
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u32 reg_offset)
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{
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return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset);
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}
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/*
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* isp_reg_writel - Write value to an OMAP3 ISP register
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* @dev: Device pointer specific to the OMAP3 ISP.
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* @reg_value: 32 bit value to write to the register.
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* @isp_mmio_range: Range to which the register offset refers to.
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* @reg_offset: Register offset to write into.
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*/
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static inline
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void isp_reg_writel(struct isp_device *isp, u32 reg_value,
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enum isp_mem_resources isp_mmio_range, u32 reg_offset)
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{
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__raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset);
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}
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/*
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* isp_reg_and - Clear individual bits in an OMAP3 ISP register
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* @dev: Device pointer specific to the OMAP3 ISP.
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* @mmio_range: Range to which the register offset refers to.
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* @reg: Register offset to work on.
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* @clr_bits: 32 bit value which would be cleared in the register.
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*/
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static inline
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void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range,
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u32 reg, u32 clr_bits)
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{
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u32 v = isp_reg_readl(isp, mmio_range, reg);
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isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg);
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}
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/*
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* isp_reg_set - Set individual bits in an OMAP3 ISP register
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* @dev: Device pointer specific to the OMAP3 ISP.
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* @mmio_range: Range to which the register offset refers to.
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* @reg: Register offset to work on.
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* @set_bits: 32 bit value which would be set in the register.
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*/
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static inline
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void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
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u32 reg, u32 set_bits)
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{
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u32 v = isp_reg_readl(isp, mmio_range, reg);
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isp_reg_writel(isp, v | set_bits, mmio_range, reg);
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}
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/*
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* isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register
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* @dev: Device pointer specific to the OMAP3 ISP.
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* @mmio_range: Range to which the register offset refers to.
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* @reg: Register offset to work on.
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* @clr_bits: 32 bit value which would be cleared in the register.
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* @set_bits: 32 bit value which would be set in the register.
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*
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* The clear operation is done first, and then the set operation.
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*/
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static inline
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void isp_reg_clr_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
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u32 reg, u32 clr_bits, u32 set_bits)
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{
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u32 v = isp_reg_readl(isp, mmio_range, reg);
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isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg);
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}
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static inline enum v4l2_buf_type
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isp_pad_buffer_type(const struct v4l2_subdev *subdev, int pad)
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{
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if (pad >= subdev->entity.num_pads)
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return 0;
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if (subdev->entity.pads[pad].flags & MEDIA_PAD_FL_SINK)
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return V4L2_BUF_TYPE_VIDEO_OUTPUT;
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else
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return V4L2_BUF_TYPE_VIDEO_CAPTURE;
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}
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#endif /* OMAP3_ISP_CORE_H */
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