168 lines
4.1 KiB
C
168 lines
4.1 KiB
C
/*
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* Copyright 2007-2009 Analog Devices Inc.
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* Philippe Gerum <rpm@xenomai.org>
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/delay.h>
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#include <asm/smp.h>
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#include <asm/dma.h>
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#include <asm/time.h>
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static DEFINE_SPINLOCK(boot_lock);
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/*
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* platform_init_cpus() - Tell the world about how many cores we
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* have. This is called while setting up the architecture support
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* (setup_arch()), so don't be too demanding here with respect to
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* available kernel services.
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*/
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void __init platform_init_cpus(void)
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{
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cpu_set(0, cpu_possible_map); /* CoreA */
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cpu_set(1, cpu_possible_map); /* CoreB */
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}
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void __init platform_prepare_cpus(unsigned int max_cpus)
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{
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int len;
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len = &coreb_trampoline_end - &coreb_trampoline_start + 1;
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BUG_ON(len > L1_CODE_LENGTH);
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dma_memcpy((void *)COREB_L1_CODE_START, &coreb_trampoline_start, len);
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/* Both cores ought to be present on a bf561! */
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cpu_set(0, cpu_present_map); /* CoreA */
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cpu_set(1, cpu_present_map); /* CoreB */
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printk(KERN_INFO "CoreB bootstrap code to SRAM %p via DMA.\n", (void *)COREB_L1_CODE_START);
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}
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int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
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{
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return -EINVAL;
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}
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void __cpuinit platform_secondary_init(unsigned int cpu)
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{
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/* Clone setup for peripheral interrupt sources from CoreA. */
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bfin_write_SICB_IMASK0(bfin_read_SIC_IMASK0());
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bfin_write_SICB_IMASK1(bfin_read_SIC_IMASK1());
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SSYNC();
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/* Clone setup for IARs from CoreA. */
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bfin_write_SICB_IAR0(bfin_read_SIC_IAR0());
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bfin_write_SICB_IAR1(bfin_read_SIC_IAR1());
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bfin_write_SICB_IAR2(bfin_read_SIC_IAR2());
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bfin_write_SICB_IAR3(bfin_read_SIC_IAR3());
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bfin_write_SICB_IAR4(bfin_read_SIC_IAR4());
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bfin_write_SICB_IAR5(bfin_read_SIC_IAR5());
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bfin_write_SICB_IAR6(bfin_read_SIC_IAR6());
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bfin_write_SICB_IAR7(bfin_read_SIC_IAR7());
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bfin_write_SICB_IWR0(IWR_DISABLE_ALL);
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bfin_write_SICB_IWR1(IWR_DISABLE_ALL);
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SSYNC();
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/* Store CPU-private information to the cpu_data array. */
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bfin_setup_cpudata(cpu);
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/* We are done with local CPU inits, unblock the boot CPU. */
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set_cpu_online(cpu, true);
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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printk(KERN_INFO "Booting Core B.\n");
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spin_lock(&boot_lock);
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if ((bfin_read_SIC_SYSCR() & COREB_SRAM_INIT) == 0) {
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/* CoreB already running, sending ipi to wakeup it */
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platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
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} else {
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/* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
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bfin_write_SIC_SYSCR(bfin_read_SIC_SYSCR() & ~COREB_SRAM_INIT);
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SSYNC();
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}
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timeout = jiffies + 1 * HZ;
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while (time_before(jiffies, timeout)) {
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if (cpu_online(cpu))
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break;
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udelay(100);
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barrier();
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}
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if (cpu_online(cpu)) {
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/* release the lock and let coreb run */
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spin_unlock(&boot_lock);
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return 0;
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} else
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panic("CPU%u: processor failed to boot\n", cpu);
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}
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void __init platform_request_ipi(irq_handler_t handler)
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{
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int ret;
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ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED,
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"Supplemental Interrupt0", handler);
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if (ret)
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panic("Cannot request supplemental interrupt 0 for IPI service");
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}
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void platform_send_ipi(cpumask_t callmap)
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{
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unsigned int cpu;
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for_each_cpu_mask(cpu, callmap) {
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BUG_ON(cpu >= 2);
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SSYNC();
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bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
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SSYNC();
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}
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}
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void platform_send_ipi_cpu(unsigned int cpu)
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{
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BUG_ON(cpu >= 2);
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SSYNC();
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bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
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SSYNC();
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}
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void platform_clear_ipi(unsigned int cpu)
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{
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BUG_ON(cpu >= 2);
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SSYNC();
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bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + cpu)));
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SSYNC();
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}
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/*
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* Setup core B's local core timer.
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* In SMP, core timer is used for clock event device.
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*/
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void __cpuinit bfin_local_timer_setup(void)
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{
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#if defined(CONFIG_TICKSOURCE_CORETMR)
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bfin_coretmr_init();
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bfin_coretmr_clockevent_init();
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get_irq_chip(IRQ_CORETMR)->unmask(IRQ_CORETMR);
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#else
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/* Power down the core timer, just to play safe. */
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bfin_write_TCNTL(0);
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#endif
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}
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