383 lines
8.4 KiB
C
383 lines
8.4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000 Ani Joshi <ajoshi@unixbox.com>
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* Copyright (C) 2000, 2001 Ralf Baechle <ralf@gnu.org>
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* Copyright (C) 2005 Ilya A. Volynets-Evenbakh <ilya@total-knowledge.com>
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* swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
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* IP32 changes by Ilya.
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*/
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/dma-mapping.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <asm/ip32/crime.h>
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/*
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* Warning on the terminology - Linux calls an uncached area coherent;
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* MIPS terminology calls memory areas with hardware maintained coherency
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* coherent.
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*/
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/*
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* Few notes.
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* 1. CPU sees memory as two chunks: 0-256M@0x0, and the rest @0x40000000+256M
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* 2. PCI sees memory as one big chunk @0x0 (or we could use 0x40000000 for native-endian)
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* 3. All other devices see memory as one big chunk at 0x40000000
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* 4. Non-PCI devices will pass NULL as struct device*
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* Thus we translate differently, depending on device.
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*/
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#define RAM_OFFSET_MASK 0x3fffffff
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void *dma_alloc_noncoherent(struct device *dev, size_t size,
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dma_addr_t * dma_handle, gfp_t gfp)
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{
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void *ret;
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/* ignore region specifiers */
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gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
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if (dev == NULL || (dev->coherent_dma_mask < 0xffffffff))
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gfp |= GFP_DMA;
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ret = (void *) __get_free_pages(gfp, get_order(size));
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if (ret != NULL) {
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unsigned long addr = virt_to_phys(ret)&RAM_OFFSET_MASK;
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memset(ret, 0, size);
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if(dev==NULL)
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addr+= CRIME_HI_MEM_BASE;
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*dma_handle = addr;
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}
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return ret;
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}
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EXPORT_SYMBOL(dma_alloc_noncoherent);
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void *dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t * dma_handle, gfp_t gfp)
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{
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void *ret;
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ret = dma_alloc_noncoherent(dev, size, dma_handle, gfp);
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if (ret) {
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dma_cache_wback_inv((unsigned long) ret, size);
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ret = UNCAC_ADDR(ret);
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}
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return ret;
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}
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EXPORT_SYMBOL(dma_alloc_coherent);
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void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
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dma_addr_t dma_handle)
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{
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free_pages((unsigned long) vaddr, get_order(size));
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}
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EXPORT_SYMBOL(dma_free_noncoherent);
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void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
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dma_addr_t dma_handle)
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{
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unsigned long addr = (unsigned long) vaddr;
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addr = CAC_ADDR(addr);
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free_pages(addr, get_order(size));
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}
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EXPORT_SYMBOL(dma_free_coherent);
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static inline void __dma_sync(unsigned long addr, size_t size,
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enum dma_data_direction direction)
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{
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switch (direction) {
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case DMA_TO_DEVICE:
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dma_cache_wback(addr, size);
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break;
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case DMA_FROM_DEVICE:
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dma_cache_inv(addr, size);
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break;
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case DMA_BIDIRECTIONAL:
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dma_cache_wback_inv(addr, size);
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break;
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default:
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BUG();
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}
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}
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dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
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enum dma_data_direction direction)
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{
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unsigned long addr = (unsigned long) ptr;
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switch (direction) {
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case DMA_TO_DEVICE:
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dma_cache_wback(addr, size);
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break;
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case DMA_FROM_DEVICE:
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dma_cache_inv(addr, size);
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break;
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case DMA_BIDIRECTIONAL:
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dma_cache_wback_inv(addr, size);
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break;
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default:
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BUG();
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}
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addr = virt_to_phys(ptr)&RAM_OFFSET_MASK;;
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if(dev == NULL)
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addr+=CRIME_HI_MEM_BASE;
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return (dma_addr_t)addr;
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}
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EXPORT_SYMBOL(dma_map_single);
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void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
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enum dma_data_direction direction)
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{
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switch (direction) {
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case DMA_TO_DEVICE:
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break;
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case DMA_FROM_DEVICE:
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break;
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case DMA_BIDIRECTIONAL:
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break;
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default:
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BUG();
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}
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}
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EXPORT_SYMBOL(dma_unmap_single);
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int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
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enum dma_data_direction direction)
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{
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int i;
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BUG_ON(direction == DMA_NONE);
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for (i = 0; i < nents; i++, sg++) {
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unsigned long addr;
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addr = (unsigned long) page_address(sg->page)+sg->offset;
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if (addr)
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__dma_sync(addr, sg->length, direction);
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addr = __pa(addr)&RAM_OFFSET_MASK;;
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if(dev == NULL)
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addr += CRIME_HI_MEM_BASE;
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sg->dma_address = (dma_addr_t)addr;
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}
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return nents;
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}
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EXPORT_SYMBOL(dma_map_sg);
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dma_addr_t dma_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size, enum dma_data_direction direction)
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{
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unsigned long addr;
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BUG_ON(direction == DMA_NONE);
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addr = (unsigned long) page_address(page) + offset;
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dma_cache_wback_inv(addr, size);
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addr = __pa(addr)&RAM_OFFSET_MASK;;
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if(dev == NULL)
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addr += CRIME_HI_MEM_BASE;
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return (dma_addr_t)addr;
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}
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EXPORT_SYMBOL(dma_map_page);
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void dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
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enum dma_data_direction direction)
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{
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BUG_ON(direction == DMA_NONE);
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if (direction != DMA_TO_DEVICE) {
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unsigned long addr;
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dma_address&=RAM_OFFSET_MASK;
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addr = dma_address + PAGE_OFFSET;
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if(dma_address>=256*1024*1024)
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addr+=CRIME_HI_MEM_BASE;
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dma_cache_wback_inv(addr, size);
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}
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}
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EXPORT_SYMBOL(dma_unmap_page);
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void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
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enum dma_data_direction direction)
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{
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unsigned long addr;
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int i;
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BUG_ON(direction == DMA_NONE);
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if (direction == DMA_TO_DEVICE)
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return;
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for (i = 0; i < nhwentries; i++, sg++) {
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addr = (unsigned long) page_address(sg->page);
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if (!addr)
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continue;
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dma_cache_wback_inv(addr + sg->offset, sg->length);
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}
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}
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EXPORT_SYMBOL(dma_unmap_sg);
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void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction direction)
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{
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unsigned long addr;
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BUG_ON(direction == DMA_NONE);
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dma_handle&=RAM_OFFSET_MASK;
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addr = dma_handle + PAGE_OFFSET;
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if(dma_handle>=256*1024*1024)
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addr+=CRIME_HI_MEM_BASE;
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__dma_sync(addr, size, direction);
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}
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EXPORT_SYMBOL(dma_sync_single_for_cpu);
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void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction direction)
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{
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unsigned long addr;
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BUG_ON(direction == DMA_NONE);
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dma_handle&=RAM_OFFSET_MASK;
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addr = dma_handle + PAGE_OFFSET;
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if(dma_handle>=256*1024*1024)
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addr+=CRIME_HI_MEM_BASE;
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__dma_sync(addr, size, direction);
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}
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EXPORT_SYMBOL(dma_sync_single_for_device);
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void dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
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unsigned long offset, size_t size, enum dma_data_direction direction)
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{
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unsigned long addr;
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BUG_ON(direction == DMA_NONE);
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dma_handle&=RAM_OFFSET_MASK;
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addr = dma_handle + offset + PAGE_OFFSET;
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if(dma_handle>=256*1024*1024)
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addr+=CRIME_HI_MEM_BASE;
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__dma_sync(addr, size, direction);
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}
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EXPORT_SYMBOL(dma_sync_single_range_for_cpu);
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void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
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unsigned long offset, size_t size, enum dma_data_direction direction)
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{
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unsigned long addr;
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BUG_ON(direction == DMA_NONE);
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dma_handle&=RAM_OFFSET_MASK;
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addr = dma_handle + offset + PAGE_OFFSET;
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if(dma_handle>=256*1024*1024)
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addr+=CRIME_HI_MEM_BASE;
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__dma_sync(addr, size, direction);
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}
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EXPORT_SYMBOL(dma_sync_single_range_for_device);
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void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
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enum dma_data_direction direction)
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{
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int i;
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BUG_ON(direction == DMA_NONE);
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/* Make sure that gcc doesn't leave the empty loop body. */
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for (i = 0; i < nelems; i++, sg++)
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__dma_sync((unsigned long)page_address(sg->page),
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sg->length, direction);
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}
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EXPORT_SYMBOL(dma_sync_sg_for_cpu);
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void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems,
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enum dma_data_direction direction)
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{
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int i;
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BUG_ON(direction == DMA_NONE);
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/* Make sure that gcc doesn't leave the empty loop body. */
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for (i = 0; i < nelems; i++, sg++)
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__dma_sync((unsigned long)page_address(sg->page),
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sg->length, direction);
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}
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EXPORT_SYMBOL(dma_sync_sg_for_device);
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int dma_mapping_error(dma_addr_t dma_addr)
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{
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return 0;
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}
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EXPORT_SYMBOL(dma_mapping_error);
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int dma_supported(struct device *dev, u64 mask)
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{
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/*
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* we fall back to GFP_DMA when the mask isn't all 1s,
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* so we can't guarantee allocations that must be
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* within a tighter range than GFP_DMA..
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*/
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if (mask < 0x00ffffff)
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return 0;
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return 1;
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}
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EXPORT_SYMBOL(dma_supported);
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int dma_is_consistent(dma_addr_t dma_addr)
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{
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return 1;
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}
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EXPORT_SYMBOL(dma_is_consistent);
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void dma_cache_sync(void *vaddr, size_t size, enum dma_data_direction direction)
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{
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if (direction == DMA_NONE)
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return;
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dma_cache_wback_inv((unsigned long)vaddr, size);
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}
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EXPORT_SYMBOL(dma_cache_sync);
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