652 lines
16 KiB
C
652 lines
16 KiB
C
/*
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* Copyright(c) 2007 Atheros Corporation. All rights reserved.
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*
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* Derived from Intel e1000 driver
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* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/mii.h>
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#include <linux/crc32.h>
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#include "atl1e.h"
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/*
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* check_eeprom_exist
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* return 0 if eeprom exist
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*/
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int atl1e_check_eeprom_exist(struct atl1e_hw *hw)
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{
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u32 value;
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value = AT_READ_REG(hw, REG_SPI_FLASH_CTRL);
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if (value & SPI_FLASH_CTRL_EN_VPD) {
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value &= ~SPI_FLASH_CTRL_EN_VPD;
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AT_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
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}
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value = AT_READ_REGW(hw, REG_PCIE_CAP_LIST);
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return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
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}
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void atl1e_hw_set_mac_addr(struct atl1e_hw *hw)
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{
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u32 value;
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/*
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* 00-0B-6A-F6-00-DC
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* 0: 6AF600DC 1: 000B
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* low dword
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*/
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value = (((u32)hw->mac_addr[2]) << 24) |
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(((u32)hw->mac_addr[3]) << 16) |
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(((u32)hw->mac_addr[4]) << 8) |
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(((u32)hw->mac_addr[5])) ;
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AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
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/* hight dword */
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value = (((u32)hw->mac_addr[0]) << 8) |
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(((u32)hw->mac_addr[1])) ;
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AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
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}
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/*
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* atl1e_get_permanent_address
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* return 0 if get valid mac address,
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*/
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static int atl1e_get_permanent_address(struct atl1e_hw *hw)
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{
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u32 addr[2];
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u32 i;
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u32 twsi_ctrl_data;
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u8 eth_addr[ETH_ALEN];
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if (is_valid_ether_addr(hw->perm_mac_addr))
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return 0;
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/* init */
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addr[0] = addr[1] = 0;
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if (!atl1e_check_eeprom_exist(hw)) {
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/* eeprom exist */
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twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL);
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twsi_ctrl_data |= TWSI_CTRL_SW_LDSTART;
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AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data);
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for (i = 0; i < AT_TWSI_EEPROM_TIMEOUT; i++) {
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msleep(10);
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twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL);
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if ((twsi_ctrl_data & TWSI_CTRL_SW_LDSTART) == 0)
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break;
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}
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if (i >= AT_TWSI_EEPROM_TIMEOUT)
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return AT_ERR_TIMEOUT;
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}
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/* maybe MAC-address is from BIOS */
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addr[0] = AT_READ_REG(hw, REG_MAC_STA_ADDR);
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addr[1] = AT_READ_REG(hw, REG_MAC_STA_ADDR + 4);
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*(u32 *) ð_addr[2] = swab32(addr[0]);
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*(u16 *) ð_addr[0] = swab16(*(u16 *)&addr[1]);
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if (is_valid_ether_addr(eth_addr)) {
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memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
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return 0;
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}
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return AT_ERR_EEPROM;
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}
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bool atl1e_write_eeprom(struct atl1e_hw *hw, u32 offset, u32 value)
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{
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return true;
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}
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bool atl1e_read_eeprom(struct atl1e_hw *hw, u32 offset, u32 *p_value)
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{
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int i;
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u32 control;
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if (offset & 3)
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return false; /* address do not align */
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AT_WRITE_REG(hw, REG_VPD_DATA, 0);
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control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
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AT_WRITE_REG(hw, REG_VPD_CAP, control);
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for (i = 0; i < 10; i++) {
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msleep(2);
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control = AT_READ_REG(hw, REG_VPD_CAP);
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if (control & VPD_CAP_VPD_FLAG)
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break;
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}
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if (control & VPD_CAP_VPD_FLAG) {
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*p_value = AT_READ_REG(hw, REG_VPD_DATA);
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return true;
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}
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return false; /* timeout */
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}
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void atl1e_force_ps(struct atl1e_hw *hw)
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{
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AT_WRITE_REGW(hw, REG_GPHY_CTRL,
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GPHY_CTRL_PW_WOL_DIS | GPHY_CTRL_EXT_RESET);
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}
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/*
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* Reads the adapter's MAC address from the EEPROM
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*
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* hw - Struct containing variables accessed by shared code
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*/
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int atl1e_read_mac_addr(struct atl1e_hw *hw)
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{
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int err = 0;
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err = atl1e_get_permanent_address(hw);
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if (err)
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return AT_ERR_EEPROM;
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memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr));
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return 0;
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}
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/*
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* atl1e_hash_mc_addr
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* purpose
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* set hash value for a multicast address
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*/
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u32 atl1e_hash_mc_addr(struct atl1e_hw *hw, u8 *mc_addr)
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{
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u32 crc32;
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u32 value = 0;
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int i;
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crc32 = ether_crc_le(6, mc_addr);
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for (i = 0; i < 32; i++)
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value |= (((crc32 >> i) & 1) << (31 - i));
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return value;
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}
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/*
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* Sets the bit in the multicast table corresponding to the hash value.
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* hw - Struct containing variables accessed by shared code
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* hash_value - Multicast address hash value
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*/
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void atl1e_hash_set(struct atl1e_hw *hw, u32 hash_value)
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{
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u32 hash_bit, hash_reg;
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u32 mta;
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/*
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* The HASH Table is a register array of 2 32-bit registers.
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* It is treated like an array of 64 bits. We want to set
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* bit BitArray[hash_value]. So we figure out what register
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* the bit is in, read it, OR in the new bit, then write
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* back the new value. The register is determined by the
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* upper 7 bits of the hash value and the bit within that
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* register are determined by the lower 5 bits of the value.
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*/
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hash_reg = (hash_value >> 31) & 0x1;
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hash_bit = (hash_value >> 26) & 0x1F;
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mta = AT_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
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mta |= (1 << hash_bit);
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AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
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}
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/*
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* Reads the value from a PHY register
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* hw - Struct containing variables accessed by shared code
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* reg_addr - address of the PHY register to read
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*/
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int atl1e_read_phy_reg(struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data)
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{
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u32 val;
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int i;
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val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
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MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW |
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MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
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AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
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wmb();
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for (i = 0; i < MDIO_WAIT_TIMES; i++) {
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udelay(2);
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val = AT_READ_REG(hw, REG_MDIO_CTRL);
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if (!(val & (MDIO_START | MDIO_BUSY)))
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break;
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wmb();
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}
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if (!(val & (MDIO_START | MDIO_BUSY))) {
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*phy_data = (u16)val;
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return 0;
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}
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return AT_ERR_PHY;
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}
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/*
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* Writes a value to a PHY register
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* hw - Struct containing variables accessed by shared code
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* reg_addr - address of the PHY register to write
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* data - data to write to the PHY
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*/
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int atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data)
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{
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int i;
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u32 val;
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val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
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(reg_addr&MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
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MDIO_SUP_PREAMBLE |
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MDIO_START |
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MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
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AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
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wmb();
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for (i = 0; i < MDIO_WAIT_TIMES; i++) {
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udelay(2);
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val = AT_READ_REG(hw, REG_MDIO_CTRL);
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if (!(val & (MDIO_START | MDIO_BUSY)))
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break;
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wmb();
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}
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if (!(val & (MDIO_START | MDIO_BUSY)))
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return 0;
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return AT_ERR_PHY;
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}
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/*
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* atl1e_init_pcie - init PCIE module
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*/
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static void atl1e_init_pcie(struct atl1e_hw *hw)
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{
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u32 value;
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/* comment 2lines below to save more power when sususpend
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value = LTSSM_TEST_MODE_DEF;
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AT_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
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*/
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/* pcie flow control mode change */
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value = AT_READ_REG(hw, 0x1008);
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value |= 0x8000;
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AT_WRITE_REG(hw, 0x1008, value);
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}
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/*
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* Configures PHY autoneg and flow control advertisement settings
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*
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* hw - Struct containing variables accessed by shared code
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*/
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static int atl1e_phy_setup_autoneg_adv(struct atl1e_hw *hw)
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{
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s32 ret_val;
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u16 mii_autoneg_adv_reg;
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u16 mii_1000t_ctrl_reg;
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if (0 != hw->mii_autoneg_adv_reg)
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return 0;
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/* Read the MII Auto-Neg Advertisement Register (Address 4/9). */
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mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
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mii_1000t_ctrl_reg = MII_AT001_CR_1000T_DEFAULT_CAP_MASK;
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/*
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* Need to parse autoneg_advertised and set up
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* the appropriate PHY registers. First we will parse for
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* autoneg_advertised software override. Since we can advertise
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* a plethora of combinations, we need to check each bit
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* individually.
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*/
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/*
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* First we clear all the 10/100 mb speed bits in the Auto-Neg
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* Advertisement Register (Address 4) and the 1000 mb speed bits in
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* the 1000Base-T control Register (Address 9).
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*/
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mii_autoneg_adv_reg &= ~ADVERTISE_ALL;
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mii_1000t_ctrl_reg &= ~MII_AT001_CR_1000T_SPEED_MASK;
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/*
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* Need to parse MediaType and setup the
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* appropriate PHY registers.
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*/
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switch (hw->media_type) {
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case MEDIA_TYPE_AUTO_SENSOR:
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mii_autoneg_adv_reg |= ADVERTISE_ALL;
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hw->autoneg_advertised = ADVERTISE_ALL;
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if (hw->nic_type == athr_l1e) {
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mii_1000t_ctrl_reg |= ADVERTISE_1000FULL;
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hw->autoneg_advertised |= ADVERTISE_1000_FULL;
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}
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break;
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case MEDIA_TYPE_100M_FULL:
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mii_autoneg_adv_reg |= ADVERTISE_100FULL;
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hw->autoneg_advertised = ADVERTISE_100_FULL;
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break;
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case MEDIA_TYPE_100M_HALF:
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mii_autoneg_adv_reg |= ADVERTISE_100_HALF;
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hw->autoneg_advertised = ADVERTISE_100_HALF;
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break;
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case MEDIA_TYPE_10M_FULL:
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mii_autoneg_adv_reg |= ADVERTISE_10_FULL;
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hw->autoneg_advertised = ADVERTISE_10_FULL;
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break;
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default:
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mii_autoneg_adv_reg |= ADVERTISE_10_HALF;
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hw->autoneg_advertised = ADVERTISE_10_HALF;
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break;
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}
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/* flow control fixed to enable all */
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mii_autoneg_adv_reg |= (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
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hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
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hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
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ret_val = atl1e_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
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if (ret_val)
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return ret_val;
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if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) {
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ret_val = atl1e_write_phy_reg(hw, MII_CTRL1000,
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mii_1000t_ctrl_reg);
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if (ret_val)
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return ret_val;
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}
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return 0;
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}
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/*
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* Resets the PHY and make all config validate
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*
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* hw - Struct containing variables accessed by shared code
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*
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* Sets bit 15 and 12 of the MII control regiser (for F001 bug)
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*/
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int atl1e_phy_commit(struct atl1e_hw *hw)
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{
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struct atl1e_adapter *adapter = hw->adapter;
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int ret_val;
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u16 phy_data;
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phy_data = BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART;
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ret_val = atl1e_write_phy_reg(hw, MII_BMCR, phy_data);
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if (ret_val) {
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u32 val;
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int i;
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/**************************************
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* pcie serdes link may be down !
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**************************************/
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for (i = 0; i < 25; i++) {
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msleep(1);
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val = AT_READ_REG(hw, REG_MDIO_CTRL);
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if (!(val & (MDIO_START | MDIO_BUSY)))
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break;
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}
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if (0 != (val & (MDIO_START | MDIO_BUSY))) {
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netdev_err(adapter->netdev,
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"pcie linkdown at least for 25ms\n");
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return ret_val;
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}
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netdev_err(adapter->netdev, "pcie linkup after %d ms\n", i);
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}
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return 0;
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}
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int atl1e_phy_init(struct atl1e_hw *hw)
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{
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struct atl1e_adapter *adapter = hw->adapter;
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s32 ret_val;
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u16 phy_val;
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if (hw->phy_configured) {
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if (hw->re_autoneg) {
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hw->re_autoneg = false;
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return atl1e_restart_autoneg(hw);
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}
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return 0;
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}
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/* RESET GPHY Core */
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AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT);
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msleep(2);
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AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT |
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GPHY_CTRL_EXT_RESET);
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msleep(2);
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/* patches */
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/* p1. eable hibernation mode */
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ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0xB);
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if (ret_val)
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return ret_val;
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ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0xBC00);
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if (ret_val)
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return ret_val;
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/* p2. set Class A/B for all modes */
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ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0);
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if (ret_val)
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return ret_val;
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phy_val = 0x02ef;
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/* remove Class AB */
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/* phy_val = hw->emi_ca ? 0x02ef : 0x02df; */
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ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, phy_val);
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if (ret_val)
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return ret_val;
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/* p3. 10B ??? */
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ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x12);
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if (ret_val)
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return ret_val;
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ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x4C04);
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if (ret_val)
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return ret_val;
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/* p4. 1000T power */
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ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x4);
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if (ret_val)
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return ret_val;
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ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x8BBB);
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if (ret_val)
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return ret_val;
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ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x5);
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if (ret_val)
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return ret_val;
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ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x2C46);
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if (ret_val)
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return ret_val;
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msleep(1);
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/*Enable PHY LinkChange Interrupt */
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ret_val = atl1e_write_phy_reg(hw, MII_INT_CTRL, 0xC00);
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if (ret_val) {
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netdev_err(adapter->netdev,
|
|
"Error enable PHY linkChange Interrupt\n");
|
|
return ret_val;
|
|
}
|
|
/* setup AutoNeg parameters */
|
|
ret_val = atl1e_phy_setup_autoneg_adv(hw);
|
|
if (ret_val) {
|
|
netdev_err(adapter->netdev,
|
|
"Error Setting up Auto-Negotiation\n");
|
|
return ret_val;
|
|
}
|
|
/* SW.Reset & En-Auto-Neg to restart Auto-Neg*/
|
|
netdev_dbg(adapter->netdev, "Restarting Auto-Negotiation\n");
|
|
ret_val = atl1e_phy_commit(hw);
|
|
if (ret_val) {
|
|
netdev_err(adapter->netdev, "Error resetting the phy\n");
|
|
return ret_val;
|
|
}
|
|
|
|
hw->phy_configured = true;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Reset the transmit and receive units; mask and clear all interrupts.
|
|
* hw - Struct containing variables accessed by shared code
|
|
* return : 0 or idle status (if error)
|
|
*/
|
|
int atl1e_reset_hw(struct atl1e_hw *hw)
|
|
{
|
|
struct atl1e_adapter *adapter = hw->adapter;
|
|
struct pci_dev *pdev = adapter->pdev;
|
|
|
|
u32 idle_status_data = 0;
|
|
u16 pci_cfg_cmd_word = 0;
|
|
int timeout = 0;
|
|
|
|
/* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
|
|
pci_read_config_word(pdev, PCI_REG_COMMAND, &pci_cfg_cmd_word);
|
|
if ((pci_cfg_cmd_word & (CMD_IO_SPACE |
|
|
CMD_MEMORY_SPACE | CMD_BUS_MASTER))
|
|
!= (CMD_IO_SPACE | CMD_MEMORY_SPACE | CMD_BUS_MASTER)) {
|
|
pci_cfg_cmd_word |= (CMD_IO_SPACE |
|
|
CMD_MEMORY_SPACE | CMD_BUS_MASTER);
|
|
pci_write_config_word(pdev, PCI_REG_COMMAND, pci_cfg_cmd_word);
|
|
}
|
|
|
|
/*
|
|
* Issue Soft Reset to the MAC. This will reset the chip's
|
|
* transmit, receive, DMA. It will not effect
|
|
* the current PCI configuration. The global reset bit is self-
|
|
* clearing, and should clear within a microsecond.
|
|
*/
|
|
AT_WRITE_REG(hw, REG_MASTER_CTRL,
|
|
MASTER_CTRL_LED_MODE | MASTER_CTRL_SOFT_RST);
|
|
wmb();
|
|
msleep(1);
|
|
|
|
/* Wait at least 10ms for All module to be Idle */
|
|
for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
|
|
idle_status_data = AT_READ_REG(hw, REG_IDLE_STATUS);
|
|
if (idle_status_data == 0)
|
|
break;
|
|
msleep(1);
|
|
cpu_relax();
|
|
}
|
|
|
|
if (timeout >= AT_HW_MAX_IDLE_DELAY) {
|
|
netdev_err(adapter->netdev,
|
|
"MAC state machine can't be idle since disabled for 10ms second\n");
|
|
return AT_ERR_TIMEOUT;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* Performs basic configuration of the adapter.
|
|
*
|
|
* hw - Struct containing variables accessed by shared code
|
|
* Assumes that the controller has previously been reset and is in a
|
|
* post-reset uninitialized state. Initializes multicast table,
|
|
* and Calls routines to setup link
|
|
* Leaves the transmit and receive units disabled and uninitialized.
|
|
*/
|
|
int atl1e_init_hw(struct atl1e_hw *hw)
|
|
{
|
|
s32 ret_val = 0;
|
|
|
|
atl1e_init_pcie(hw);
|
|
|
|
/* Zero out the Multicast HASH table */
|
|
/* clear the old settings from the multicast hash table */
|
|
AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
|
|
AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
|
|
|
|
ret_val = atl1e_phy_init(hw);
|
|
|
|
return ret_val;
|
|
}
|
|
|
|
/*
|
|
* Detects the current speed and duplex settings of the hardware.
|
|
*
|
|
* hw - Struct containing variables accessed by shared code
|
|
* speed - Speed of the connection
|
|
* duplex - Duplex setting of the connection
|
|
*/
|
|
int atl1e_get_speed_and_duplex(struct atl1e_hw *hw, u16 *speed, u16 *duplex)
|
|
{
|
|
int err;
|
|
u16 phy_data;
|
|
|
|
/* Read PHY Specific Status Register (17) */
|
|
err = atl1e_read_phy_reg(hw, MII_AT001_PSSR, &phy_data);
|
|
if (err)
|
|
return err;
|
|
|
|
if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED))
|
|
return AT_ERR_PHY_RES;
|
|
|
|
switch (phy_data & MII_AT001_PSSR_SPEED) {
|
|
case MII_AT001_PSSR_1000MBS:
|
|
*speed = SPEED_1000;
|
|
break;
|
|
case MII_AT001_PSSR_100MBS:
|
|
*speed = SPEED_100;
|
|
break;
|
|
case MII_AT001_PSSR_10MBS:
|
|
*speed = SPEED_10;
|
|
break;
|
|
default:
|
|
return AT_ERR_PHY_SPEED;
|
|
break;
|
|
}
|
|
|
|
if (phy_data & MII_AT001_PSSR_DPLX)
|
|
*duplex = FULL_DUPLEX;
|
|
else
|
|
*duplex = HALF_DUPLEX;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int atl1e_restart_autoneg(struct atl1e_hw *hw)
|
|
{
|
|
int err = 0;
|
|
|
|
err = atl1e_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
|
|
if (err)
|
|
return err;
|
|
|
|
if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) {
|
|
err = atl1e_write_phy_reg(hw, MII_CTRL1000,
|
|
hw->mii_1000t_ctrl_reg);
|
|
if (err)
|
|
return err;
|
|
}
|
|
|
|
err = atl1e_write_phy_reg(hw, MII_BMCR,
|
|
BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART);
|
|
return err;
|
|
}
|
|
|