1148 lines
26 KiB
C
1148 lines
26 KiB
C
/*
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* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <asm/arch/clock.h>
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#include <asm/div64.h>
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#include "crm_regs.h"
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#define PRE_DIV_MIN_FREQ 10000000 /* Minimum Frequency after Predivider */
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static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post)
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{
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u32 min_pre, temp_pre, old_err, err;
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if (div >= 512) {
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*pre = 8;
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*post = 64;
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} else if (div >= 64) {
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min_pre = (div - 1) / 64 + 1;
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old_err = 8;
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for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
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err = div % temp_pre;
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if (err == 0) {
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*pre = temp_pre;
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break;
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}
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err = temp_pre - err;
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if (err < old_err) {
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old_err = err;
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*pre = temp_pre;
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}
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}
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*post = (div + *pre - 1) / *pre;
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} else if (div <= 8) {
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*pre = div;
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*post = 1;
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} else {
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*pre = 1;
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*post = div;
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}
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}
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static struct clk mcu_pll_clk;
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static struct clk mcu_main_clk;
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static struct clk usb_pll_clk;
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static struct clk serial_pll_clk;
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static struct clk ipg_clk;
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static struct clk ckih_clk;
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static struct clk ahb_clk;
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static int _clk_enable(struct clk *clk)
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{
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u32 reg;
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reg = __raw_readl(clk->enable_reg);
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reg |= 3 << clk->enable_shift;
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__raw_writel(reg, clk->enable_reg);
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return 0;
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}
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static void _clk_disable(struct clk *clk)
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{
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u32 reg;
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reg = __raw_readl(clk->enable_reg);
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reg &= ~(3 << clk->enable_shift);
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__raw_writel(reg, clk->enable_reg);
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}
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static void _clk_emi_disable(struct clk *clk)
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{
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u32 reg;
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reg = __raw_readl(clk->enable_reg);
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reg &= ~(3 << clk->enable_shift);
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reg |= (1 << clk->enable_shift);
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__raw_writel(reg, clk->enable_reg);
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}
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static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
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{
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u32 reg;
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signed long pd = 1; /* Pre-divider */
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signed long mfi; /* Multiplication Factor (Integer part) */
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signed long mfn; /* Multiplication Factor (Integer part) */
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signed long mfd; /* Multiplication Factor (Denominator Part) */
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signed long tmp;
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u32 ref_freq = clk_get_rate(clk->parent);
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while (((ref_freq / pd) * 10) > rate)
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pd++;
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if ((ref_freq / pd) < PRE_DIV_MIN_FREQ)
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return -EINVAL;
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/* the ref_freq/2 in the following is to round up */
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mfi = (((rate / 2) * pd) + (ref_freq / 2)) / ref_freq;
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if (mfi < 5 || mfi > 15)
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return -EINVAL;
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/* pick a mfd value that will work
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* then solve for mfn */
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mfd = ref_freq / 50000;
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/*
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* pll_freq * pd * mfd
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* mfn = -------------------- - (mfi * mfd)
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* 2 * ref_freq
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*/
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/* the tmp/2 is for rounding */
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tmp = ref_freq / 10000;
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mfn =
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((((((rate / 2) + (tmp / 2)) / tmp) * pd) * mfd) / 10000) -
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(mfi * mfd);
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mfn = mfn & 0x3ff;
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pd--;
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mfd--;
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/* Change the Pll value */
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reg = (mfi << MXC_CCM_PCTL_MFI_OFFSET) |
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(mfn << MXC_CCM_PCTL_MFN_OFFSET) |
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(mfd << MXC_CCM_PCTL_MFD_OFFSET) | (pd << MXC_CCM_PCTL_PD_OFFSET);
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if (clk == &mcu_pll_clk)
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__raw_writel(reg, MXC_CCM_MPCTL);
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else if (clk == &usb_pll_clk)
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__raw_writel(reg, MXC_CCM_UPCTL);
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else if (clk == &serial_pll_clk)
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__raw_writel(reg, MXC_CCM_SRPCTL);
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return 0;
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}
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static unsigned long _clk_pll_get_rate(struct clk *clk)
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{
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long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
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unsigned long reg, ccmr;
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s64 temp;
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unsigned int prcs;
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ccmr = __raw_readl(MXC_CCM_CCMR);
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prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
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if (prcs == 0x1)
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ref_clk = CKIL_CLK_FREQ * 1024;
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else
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ref_clk = clk_get_rate(&ckih_clk);
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if (clk == &mcu_pll_clk) {
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if ((ccmr & MXC_CCM_CCMR_MPE) == 0)
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return ref_clk;
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if ((ccmr & MXC_CCM_CCMR_MDS) != 0)
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return ref_clk;
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reg = __raw_readl(MXC_CCM_MPCTL);
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} else if (clk == &usb_pll_clk)
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reg = __raw_readl(MXC_CCM_UPCTL);
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else if (clk == &serial_pll_clk)
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reg = __raw_readl(MXC_CCM_SRPCTL);
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else {
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BUG();
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return 0;
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}
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pdf = (reg & MXC_CCM_PCTL_PD_MASK) >> MXC_CCM_PCTL_PD_OFFSET;
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mfd = (reg & MXC_CCM_PCTL_MFD_MASK) >> MXC_CCM_PCTL_MFD_OFFSET;
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mfi = (reg & MXC_CCM_PCTL_MFI_MASK) >> MXC_CCM_PCTL_MFI_OFFSET;
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mfi = (mfi <= 5) ? 5 : mfi;
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mfn = mfn_abs = reg & MXC_CCM_PCTL_MFN_MASK;
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if (mfn >= 0x200) {
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mfn |= 0xFFFFFE00;
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mfn_abs = -mfn;
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}
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ref_clk *= 2;
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ref_clk /= pdf + 1;
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temp = (u64) ref_clk * mfn_abs;
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do_div(temp, mfd + 1);
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if (mfn < 0)
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temp = -temp;
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temp = (ref_clk * mfi) + temp;
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return temp;
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}
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static int _clk_usb_pll_enable(struct clk *clk)
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{
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u32 reg;
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reg = __raw_readl(MXC_CCM_CCMR);
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reg |= MXC_CCM_CCMR_UPE;
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__raw_writel(reg, MXC_CCM_CCMR);
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/* No lock bit on MX31, so using max time from spec */
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udelay(80);
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return 0;
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}
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static void _clk_usb_pll_disable(struct clk *clk)
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{
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u32 reg;
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reg = __raw_readl(MXC_CCM_CCMR);
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reg &= ~MXC_CCM_CCMR_UPE;
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__raw_writel(reg, MXC_CCM_CCMR);
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}
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static int _clk_serial_pll_enable(struct clk *clk)
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{
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u32 reg;
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reg = __raw_readl(MXC_CCM_CCMR);
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reg |= MXC_CCM_CCMR_SPE;
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__raw_writel(reg, MXC_CCM_CCMR);
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/* No lock bit on MX31, so using max time from spec */
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udelay(80);
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return 0;
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}
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static void _clk_serial_pll_disable(struct clk *clk)
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{
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u32 reg;
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reg = __raw_readl(MXC_CCM_CCMR);
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reg &= ~MXC_CCM_CCMR_SPE;
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__raw_writel(reg, MXC_CCM_CCMR);
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}
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#define PDR0(mask, off) ((__raw_readl(MXC_CCM_PDR0) & mask) >> off)
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#define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off)
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#define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off)
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static unsigned long _clk_mcu_main_get_rate(struct clk *clk)
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{
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u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0);
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if ((pmcr0 & MXC_CCM_PMCR0_DFSUP1) == MXC_CCM_PMCR0_DFSUP1_SPLL)
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return clk_get_rate(&serial_pll_clk);
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else
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return clk_get_rate(&mcu_pll_clk);
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}
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static unsigned long _clk_hclk_get_rate(struct clk *clk)
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{
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unsigned long max_pdf;
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max_pdf = PDR0(MXC_CCM_PDR0_MAX_PODF_MASK,
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MXC_CCM_PDR0_MAX_PODF_OFFSET);
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return clk_get_rate(clk->parent) / (max_pdf + 1);
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}
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static unsigned long _clk_ipg_get_rate(struct clk *clk)
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{
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unsigned long ipg_pdf;
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ipg_pdf = PDR0(MXC_CCM_PDR0_IPG_PODF_MASK,
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MXC_CCM_PDR0_IPG_PODF_OFFSET);
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return clk_get_rate(clk->parent) / (ipg_pdf + 1);
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}
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static unsigned long _clk_nfc_get_rate(struct clk *clk)
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{
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unsigned long nfc_pdf;
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nfc_pdf = PDR0(MXC_CCM_PDR0_NFC_PODF_MASK,
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MXC_CCM_PDR0_NFC_PODF_OFFSET);
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return clk_get_rate(clk->parent) / (nfc_pdf + 1);
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}
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static unsigned long _clk_hsp_get_rate(struct clk *clk)
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{
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unsigned long hsp_pdf;
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hsp_pdf = PDR0(MXC_CCM_PDR0_HSP_PODF_MASK,
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MXC_CCM_PDR0_HSP_PODF_OFFSET);
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return clk_get_rate(clk->parent) / (hsp_pdf + 1);
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}
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static unsigned long _clk_usb_get_rate(struct clk *clk)
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{
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unsigned long usb_pdf, usb_prepdf;
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usb_pdf = PDR1(MXC_CCM_PDR1_USB_PODF_MASK,
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MXC_CCM_PDR1_USB_PODF_OFFSET);
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usb_prepdf = PDR1(MXC_CCM_PDR1_USB_PRDF_MASK,
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MXC_CCM_PDR1_USB_PRDF_OFFSET);
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return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1);
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}
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static unsigned long _clk_csi_get_rate(struct clk *clk)
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{
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u32 reg, pre, post;
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reg = __raw_readl(MXC_CCM_PDR0);
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pre = (reg & MXC_CCM_PDR0_CSI_PRDF_MASK) >>
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MXC_CCM_PDR0_CSI_PRDF_OFFSET;
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pre++;
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post = (reg & MXC_CCM_PDR0_CSI_PODF_MASK) >>
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MXC_CCM_PDR0_CSI_PODF_OFFSET;
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post++;
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return clk_get_rate(clk->parent) / (pre * post);
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}
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static unsigned long _clk_csi_round_rate(struct clk *clk, unsigned long rate)
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{
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u32 pre, post, parent = clk_get_rate(clk->parent);
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u32 div = parent / rate;
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if (parent % rate)
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div++;
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__calc_pre_post_dividers(div, &pre, &post);
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return parent / (pre * post);
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}
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static int _clk_csi_set_rate(struct clk *clk, unsigned long rate)
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{
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u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
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div = parent / rate;
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if ((parent / div) != rate)
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return -EINVAL;
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__calc_pre_post_dividers(div, &pre, &post);
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/* Set CSI clock divider */
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reg = __raw_readl(MXC_CCM_PDR0) &
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~(MXC_CCM_PDR0_CSI_PODF_MASK | MXC_CCM_PDR0_CSI_PRDF_MASK);
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reg |= (post - 1) << MXC_CCM_PDR0_CSI_PODF_OFFSET;
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reg |= (pre - 1) << MXC_CCM_PDR0_CSI_PRDF_OFFSET;
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__raw_writel(reg, MXC_CCM_PDR0);
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return 0;
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}
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static unsigned long _clk_per_get_rate(struct clk *clk)
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{
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unsigned long per_pdf;
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per_pdf = PDR0(MXC_CCM_PDR0_PER_PODF_MASK,
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MXC_CCM_PDR0_PER_PODF_OFFSET);
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return clk_get_rate(clk->parent) / (per_pdf + 1);
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}
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static unsigned long _clk_ssi1_get_rate(struct clk *clk)
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{
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unsigned long ssi1_pdf, ssi1_prepdf;
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ssi1_pdf = PDR1(MXC_CCM_PDR1_SSI1_PODF_MASK,
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MXC_CCM_PDR1_SSI1_PODF_OFFSET);
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ssi1_prepdf = PDR1(MXC_CCM_PDR1_SSI1_PRE_PODF_MASK,
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MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET);
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return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1);
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}
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static unsigned long _clk_ssi2_get_rate(struct clk *clk)
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{
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unsigned long ssi2_pdf, ssi2_prepdf;
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ssi2_pdf = PDR1(MXC_CCM_PDR1_SSI2_PODF_MASK,
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MXC_CCM_PDR1_SSI2_PODF_OFFSET);
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ssi2_prepdf = PDR1(MXC_CCM_PDR1_SSI2_PRE_PODF_MASK,
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MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET);
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return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1);
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}
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static unsigned long _clk_firi_get_rate(struct clk *clk)
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{
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unsigned long firi_pdf, firi_prepdf;
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firi_pdf = PDR1(MXC_CCM_PDR1_FIRI_PODF_MASK,
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MXC_CCM_PDR1_FIRI_PODF_OFFSET);
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firi_prepdf = PDR1(MXC_CCM_PDR1_FIRI_PRE_PODF_MASK,
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MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET);
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return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1);
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}
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static unsigned long _clk_firi_round_rate(struct clk *clk, unsigned long rate)
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{
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u32 pre, post;
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u32 parent = clk_get_rate(clk->parent);
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u32 div = parent / rate;
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if (parent % rate)
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div++;
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__calc_pre_post_dividers(div, &pre, &post);
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return parent / (pre * post);
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}
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static int _clk_firi_set_rate(struct clk *clk, unsigned long rate)
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{
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u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
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div = parent / rate;
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if ((parent / div) != rate)
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return -EINVAL;
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__calc_pre_post_dividers(div, &pre, &post);
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/* Set FIRI clock divider */
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reg = __raw_readl(MXC_CCM_PDR1) &
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~(MXC_CCM_PDR1_FIRI_PODF_MASK | MXC_CCM_PDR1_FIRI_PRE_PODF_MASK);
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reg |= (pre - 1) << MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET;
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reg |= (post - 1) << MXC_CCM_PDR1_FIRI_PODF_OFFSET;
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__raw_writel(reg, MXC_CCM_PDR1);
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return 0;
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}
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static unsigned long _clk_mbx_get_rate(struct clk *clk)
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{
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return clk_get_rate(clk->parent) / 2;
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}
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static unsigned long _clk_mstick1_get_rate(struct clk *clk)
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{
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unsigned long msti_pdf;
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msti_pdf = PDR2(MXC_CCM_PDR2_MST1_PDF_MASK,
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MXC_CCM_PDR2_MST1_PDF_OFFSET);
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return clk_get_rate(clk->parent) / (msti_pdf + 1);
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}
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static unsigned long _clk_mstick2_get_rate(struct clk *clk)
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{
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unsigned long msti_pdf;
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msti_pdf = PDR2(MXC_CCM_PDR2_MST2_PDF_MASK,
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MXC_CCM_PDR2_MST2_PDF_OFFSET);
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return clk_get_rate(clk->parent) / (msti_pdf + 1);
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}
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static unsigned long ckih_rate;
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static unsigned long clk_ckih_get_rate(struct clk *clk)
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{
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return ckih_rate;
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}
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static struct clk ckih_clk = {
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.name = "ckih",
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.get_rate = clk_ckih_get_rate,
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};
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static unsigned long clk_ckil_get_rate(struct clk *clk)
|
|
{
|
|
return CKIL_CLK_FREQ;
|
|
}
|
|
|
|
static struct clk ckil_clk = {
|
|
.name = "ckil",
|
|
.get_rate = clk_ckil_get_rate,
|
|
};
|
|
|
|
static struct clk mcu_pll_clk = {
|
|
.name = "mcu_pll",
|
|
.parent = &ckih_clk,
|
|
.set_rate = _clk_pll_set_rate,
|
|
.get_rate = _clk_pll_get_rate,
|
|
};
|
|
|
|
static struct clk mcu_main_clk = {
|
|
.name = "mcu_main_clk",
|
|
.parent = &mcu_pll_clk,
|
|
.get_rate = _clk_mcu_main_get_rate,
|
|
};
|
|
|
|
static struct clk serial_pll_clk = {
|
|
.name = "serial_pll",
|
|
.parent = &ckih_clk,
|
|
.set_rate = _clk_pll_set_rate,
|
|
.get_rate = _clk_pll_get_rate,
|
|
.enable = _clk_serial_pll_enable,
|
|
.disable = _clk_serial_pll_disable,
|
|
};
|
|
|
|
static struct clk usb_pll_clk = {
|
|
.name = "usb_pll",
|
|
.parent = &ckih_clk,
|
|
.set_rate = _clk_pll_set_rate,
|
|
.get_rate = _clk_pll_get_rate,
|
|
.enable = _clk_usb_pll_enable,
|
|
.disable = _clk_usb_pll_disable,
|
|
};
|
|
|
|
static struct clk ahb_clk = {
|
|
.name = "ahb_clk",
|
|
.parent = &mcu_main_clk,
|
|
.get_rate = _clk_hclk_get_rate,
|
|
};
|
|
|
|
static struct clk per_clk = {
|
|
.name = "per_clk",
|
|
.parent = &usb_pll_clk,
|
|
.get_rate = _clk_per_get_rate,
|
|
};
|
|
|
|
static struct clk perclk_clk = {
|
|
.name = "perclk_clk",
|
|
.parent = &ipg_clk,
|
|
};
|
|
|
|
static struct clk cspi_clk[] = {
|
|
{
|
|
.name = "cspi_clk",
|
|
.id = 0,
|
|
.parent = &ipg_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR2,
|
|
.enable_shift = MXC_CCM_CGR2_CSPI1_OFFSET,
|
|
.disable = _clk_disable,},
|
|
{
|
|
.name = "cspi_clk",
|
|
.id = 1,
|
|
.parent = &ipg_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR2,
|
|
.enable_shift = MXC_CCM_CGR2_CSPI2_OFFSET,
|
|
.disable = _clk_disable,},
|
|
{
|
|
.name = "cspi_clk",
|
|
.id = 2,
|
|
.parent = &ipg_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR0,
|
|
.enable_shift = MXC_CCM_CGR0_CSPI3_OFFSET,
|
|
.disable = _clk_disable,},
|
|
};
|
|
|
|
static struct clk ipg_clk = {
|
|
.name = "ipg_clk",
|
|
.parent = &ahb_clk,
|
|
.get_rate = _clk_ipg_get_rate,
|
|
};
|
|
|
|
static struct clk emi_clk = {
|
|
.name = "emi_clk",
|
|
.parent = &ahb_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR2,
|
|
.enable_shift = MXC_CCM_CGR2_EMI_OFFSET,
|
|
.disable = _clk_emi_disable,
|
|
};
|
|
|
|
static struct clk gpt_clk = {
|
|
.name = "gpt_clk",
|
|
.parent = &perclk_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR0,
|
|
.enable_shift = MXC_CCM_CGR0_GPT_OFFSET,
|
|
.disable = _clk_disable,
|
|
};
|
|
|
|
static struct clk pwm_clk = {
|
|
.name = "pwm_clk",
|
|
.parent = &perclk_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR0,
|
|
.enable_shift = MXC_CCM_CGR1_PWM_OFFSET,
|
|
.disable = _clk_disable,
|
|
};
|
|
|
|
static struct clk epit_clk[] = {
|
|
{
|
|
.name = "epit_clk",
|
|
.id = 0,
|
|
.parent = &perclk_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR0,
|
|
.enable_shift = MXC_CCM_CGR0_EPIT1_OFFSET,
|
|
.disable = _clk_disable,},
|
|
{
|
|
.name = "epit_clk",
|
|
.id = 1,
|
|
.parent = &perclk_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR0,
|
|
.enable_shift = MXC_CCM_CGR0_EPIT2_OFFSET,
|
|
.disable = _clk_disable,},
|
|
};
|
|
|
|
static struct clk nfc_clk = {
|
|
.name = "nfc_clk",
|
|
.parent = &ahb_clk,
|
|
.get_rate = _clk_nfc_get_rate,
|
|
};
|
|
|
|
static struct clk scc_clk = {
|
|
.name = "scc_clk",
|
|
.parent = &ipg_clk,
|
|
};
|
|
|
|
static struct clk ipu_clk = {
|
|
.name = "ipu_clk",
|
|
.parent = &mcu_main_clk,
|
|
.get_rate = _clk_hsp_get_rate,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR1,
|
|
.enable_shift = MXC_CCM_CGR1_IPU_OFFSET,
|
|
.disable = _clk_disable,
|
|
};
|
|
|
|
static struct clk kpp_clk = {
|
|
.name = "kpp_clk",
|
|
.parent = &ipg_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR1,
|
|
.enable_shift = MXC_CCM_CGR1_KPP_OFFSET,
|
|
.disable = _clk_disable,
|
|
};
|
|
|
|
static struct clk wdog_clk = {
|
|
.name = "wdog_clk",
|
|
.parent = &ipg_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR1,
|
|
.enable_shift = MXC_CCM_CGR1_WDOG_OFFSET,
|
|
.disable = _clk_disable,
|
|
};
|
|
static struct clk rtc_clk = {
|
|
.name = "rtc_clk",
|
|
.parent = &ipg_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR1,
|
|
.enable_shift = MXC_CCM_CGR1_RTC_OFFSET,
|
|
.disable = _clk_disable,
|
|
};
|
|
|
|
static struct clk usb_clk[] = {
|
|
{
|
|
.name = "usb_clk",
|
|
.parent = &usb_pll_clk,
|
|
.get_rate = _clk_usb_get_rate,},
|
|
{
|
|
.name = "usb_ahb_clk",
|
|
.parent = &ahb_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR1,
|
|
.enable_shift = MXC_CCM_CGR1_USBOTG_OFFSET,
|
|
.disable = _clk_disable,},
|
|
};
|
|
|
|
static struct clk csi_clk = {
|
|
.name = "csi_clk",
|
|
.parent = &serial_pll_clk,
|
|
.get_rate = _clk_csi_get_rate,
|
|
.round_rate = _clk_csi_round_rate,
|
|
.set_rate = _clk_csi_set_rate,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR1,
|
|
.enable_shift = MXC_CCM_CGR1_CSI_OFFSET,
|
|
.disable = _clk_disable,
|
|
};
|
|
|
|
static struct clk uart_clk[] = {
|
|
{
|
|
.name = "uart_clk",
|
|
.id = 0,
|
|
.parent = &perclk_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR0,
|
|
.enable_shift = MXC_CCM_CGR0_UART1_OFFSET,
|
|
.disable = _clk_disable,},
|
|
{
|
|
.name = "uart_clk",
|
|
.id = 1,
|
|
.parent = &perclk_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR0,
|
|
.enable_shift = MXC_CCM_CGR0_UART2_OFFSET,
|
|
.disable = _clk_disable,},
|
|
{
|
|
.name = "uart_clk",
|
|
.id = 2,
|
|
.parent = &perclk_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR1,
|
|
.enable_shift = MXC_CCM_CGR1_UART3_OFFSET,
|
|
.disable = _clk_disable,},
|
|
{
|
|
.name = "uart_clk",
|
|
.id = 3,
|
|
.parent = &perclk_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR1,
|
|
.enable_shift = MXC_CCM_CGR1_UART4_OFFSET,
|
|
.disable = _clk_disable,},
|
|
{
|
|
.name = "uart_clk",
|
|
.id = 4,
|
|
.parent = &perclk_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR1,
|
|
.enable_shift = MXC_CCM_CGR1_UART5_OFFSET,
|
|
.disable = _clk_disable,},
|
|
};
|
|
|
|
static struct clk i2c_clk[] = {
|
|
{
|
|
.name = "i2c_clk",
|
|
.id = 0,
|
|
.parent = &perclk_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR0,
|
|
.enable_shift = MXC_CCM_CGR0_I2C1_OFFSET,
|
|
.disable = _clk_disable,},
|
|
{
|
|
.name = "i2c_clk",
|
|
.id = 1,
|
|
.parent = &perclk_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR0,
|
|
.enable_shift = MXC_CCM_CGR0_I2C2_OFFSET,
|
|
.disable = _clk_disable,},
|
|
{
|
|
.name = "i2c_clk",
|
|
.id = 2,
|
|
.parent = &perclk_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR0,
|
|
.enable_shift = MXC_CCM_CGR0_I2C3_OFFSET,
|
|
.disable = _clk_disable,},
|
|
};
|
|
|
|
static struct clk owire_clk = {
|
|
.name = "owire_clk",
|
|
.parent = &perclk_clk,
|
|
.enable_reg = MXC_CCM_CGR1,
|
|
.enable_shift = MXC_CCM_CGR1_OWIRE_OFFSET,
|
|
.enable = _clk_enable,
|
|
.disable = _clk_disable,
|
|
};
|
|
|
|
static struct clk sdhc_clk[] = {
|
|
{
|
|
.name = "sdhc_clk",
|
|
.id = 0,
|
|
.parent = &perclk_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR0,
|
|
.enable_shift = MXC_CCM_CGR0_SD_MMC1_OFFSET,
|
|
.disable = _clk_disable,},
|
|
{
|
|
.name = "sdhc_clk",
|
|
.id = 1,
|
|
.parent = &perclk_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR0,
|
|
.enable_shift = MXC_CCM_CGR0_SD_MMC2_OFFSET,
|
|
.disable = _clk_disable,},
|
|
};
|
|
|
|
static struct clk ssi_clk[] = {
|
|
{
|
|
.name = "ssi_clk",
|
|
.parent = &serial_pll_clk,
|
|
.get_rate = _clk_ssi1_get_rate,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR0,
|
|
.enable_shift = MXC_CCM_CGR0_SSI1_OFFSET,
|
|
.disable = _clk_disable,},
|
|
{
|
|
.name = "ssi_clk",
|
|
.id = 1,
|
|
.parent = &serial_pll_clk,
|
|
.get_rate = _clk_ssi2_get_rate,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR2,
|
|
.enable_shift = MXC_CCM_CGR2_SSI2_OFFSET,
|
|
.disable = _clk_disable,},
|
|
};
|
|
|
|
static struct clk firi_clk = {
|
|
.name = "firi_clk",
|
|
.parent = &usb_pll_clk,
|
|
.round_rate = _clk_firi_round_rate,
|
|
.set_rate = _clk_firi_set_rate,
|
|
.get_rate = _clk_firi_get_rate,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR2,
|
|
.enable_shift = MXC_CCM_CGR2_FIRI_OFFSET,
|
|
.disable = _clk_disable,
|
|
};
|
|
|
|
static struct clk ata_clk = {
|
|
.name = "ata_clk",
|
|
.parent = &ipg_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR0,
|
|
.enable_shift = MXC_CCM_CGR0_ATA_OFFSET,
|
|
.disable = _clk_disable,
|
|
};
|
|
|
|
static struct clk mbx_clk = {
|
|
.name = "mbx_clk",
|
|
.parent = &ahb_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR2,
|
|
.enable_shift = MXC_CCM_CGR2_GACC_OFFSET,
|
|
.get_rate = _clk_mbx_get_rate,
|
|
};
|
|
|
|
static struct clk vpu_clk = {
|
|
.name = "vpu_clk",
|
|
.parent = &ahb_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR2,
|
|
.enable_shift = MXC_CCM_CGR2_GACC_OFFSET,
|
|
.get_rate = _clk_mbx_get_rate,
|
|
};
|
|
|
|
static struct clk rtic_clk = {
|
|
.name = "rtic_clk",
|
|
.parent = &ahb_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR2,
|
|
.enable_shift = MXC_CCM_CGR2_RTIC_OFFSET,
|
|
.disable = _clk_disable,
|
|
};
|
|
|
|
static struct clk rng_clk = {
|
|
.name = "rng_clk",
|
|
.parent = &ipg_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR0,
|
|
.enable_shift = MXC_CCM_CGR0_RNG_OFFSET,
|
|
.disable = _clk_disable,
|
|
};
|
|
|
|
static struct clk sdma_clk[] = {
|
|
{
|
|
.name = "sdma_ahb_clk",
|
|
.parent = &ahb_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR0,
|
|
.enable_shift = MXC_CCM_CGR0_SDMA_OFFSET,
|
|
.disable = _clk_disable,},
|
|
{
|
|
.name = "sdma_ipg_clk",
|
|
.parent = &ipg_clk,}
|
|
};
|
|
|
|
static struct clk mpeg4_clk = {
|
|
.name = "mpeg4_clk",
|
|
.parent = &ahb_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR1,
|
|
.enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET,
|
|
.disable = _clk_disable,
|
|
};
|
|
|
|
static struct clk vl2cc_clk = {
|
|
.name = "vl2cc_clk",
|
|
.parent = &ahb_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR1,
|
|
.enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET,
|
|
.disable = _clk_disable,
|
|
};
|
|
|
|
static struct clk mstick_clk[] = {
|
|
{
|
|
.name = "mstick_clk",
|
|
.id = 0,
|
|
.parent = &usb_pll_clk,
|
|
.get_rate = _clk_mstick1_get_rate,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR1,
|
|
.enable_shift = MXC_CCM_CGR1_MEMSTICK1_OFFSET,
|
|
.disable = _clk_disable,},
|
|
{
|
|
.name = "mstick_clk",
|
|
.id = 1,
|
|
.parent = &usb_pll_clk,
|
|
.get_rate = _clk_mstick2_get_rate,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR1,
|
|
.enable_shift = MXC_CCM_CGR1_MEMSTICK2_OFFSET,
|
|
.disable = _clk_disable,},
|
|
};
|
|
|
|
static struct clk iim_clk = {
|
|
.name = "iim_clk",
|
|
.parent = &ipg_clk,
|
|
.enable = _clk_enable,
|
|
.enable_reg = MXC_CCM_CGR0,
|
|
.enable_shift = MXC_CCM_CGR0_IIM_OFFSET,
|
|
.disable = _clk_disable,
|
|
};
|
|
|
|
static unsigned long _clk_cko1_round_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
u32 div, parent = clk_get_rate(clk->parent);
|
|
|
|
div = parent / rate;
|
|
if (parent % rate)
|
|
div++;
|
|
|
|
if (div > 8)
|
|
div = 16;
|
|
else if (div > 4)
|
|
div = 8;
|
|
else if (div > 2)
|
|
div = 4;
|
|
|
|
return parent / div;
|
|
}
|
|
|
|
static int _clk_cko1_set_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
u32 reg, div, parent = clk_get_rate(clk->parent);
|
|
|
|
div = parent / rate;
|
|
|
|
if (div == 16)
|
|
div = 4;
|
|
else if (div == 8)
|
|
div = 3;
|
|
else if (div == 4)
|
|
div = 2;
|
|
else if (div == 2)
|
|
div = 1;
|
|
else if (div == 1)
|
|
div = 0;
|
|
else
|
|
return -EINVAL;
|
|
|
|
reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOUTDIV_MASK;
|
|
reg |= div << MXC_CCM_COSR_CLKOUTDIV_OFFSET;
|
|
__raw_writel(reg, MXC_CCM_COSR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static unsigned long _clk_cko1_get_rate(struct clk *clk)
|
|
{
|
|
u32 div;
|
|
|
|
div = __raw_readl(MXC_CCM_COSR) & MXC_CCM_COSR_CLKOUTDIV_MASK >>
|
|
MXC_CCM_COSR_CLKOUTDIV_OFFSET;
|
|
|
|
return clk_get_rate(clk->parent) / (1 << div);
|
|
}
|
|
|
|
static int _clk_cko1_set_parent(struct clk *clk, struct clk *parent)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOSEL_MASK;
|
|
|
|
if (parent == &mcu_main_clk)
|
|
reg |= 0 << MXC_CCM_COSR_CLKOSEL_OFFSET;
|
|
else if (parent == &ipg_clk)
|
|
reg |= 1 << MXC_CCM_COSR_CLKOSEL_OFFSET;
|
|
else if (parent == &usb_pll_clk)
|
|
reg |= 2 << MXC_CCM_COSR_CLKOSEL_OFFSET;
|
|
else if (parent == mcu_main_clk.parent)
|
|
reg |= 3 << MXC_CCM_COSR_CLKOSEL_OFFSET;
|
|
else if (parent == &ahb_clk)
|
|
reg |= 5 << MXC_CCM_COSR_CLKOSEL_OFFSET;
|
|
else if (parent == &serial_pll_clk)
|
|
reg |= 7 << MXC_CCM_COSR_CLKOSEL_OFFSET;
|
|
else if (parent == &ckih_clk)
|
|
reg |= 8 << MXC_CCM_COSR_CLKOSEL_OFFSET;
|
|
else if (parent == &emi_clk)
|
|
reg |= 9 << MXC_CCM_COSR_CLKOSEL_OFFSET;
|
|
else if (parent == &ipu_clk)
|
|
reg |= 0xA << MXC_CCM_COSR_CLKOSEL_OFFSET;
|
|
else if (parent == &nfc_clk)
|
|
reg |= 0xB << MXC_CCM_COSR_CLKOSEL_OFFSET;
|
|
else if (parent == &uart_clk[0])
|
|
reg |= 0xC << MXC_CCM_COSR_CLKOSEL_OFFSET;
|
|
else
|
|
return -EINVAL;
|
|
|
|
__raw_writel(reg, MXC_CCM_COSR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int _clk_cko1_enable(struct clk *clk)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = __raw_readl(MXC_CCM_COSR) | MXC_CCM_COSR_CLKOEN;
|
|
__raw_writel(reg, MXC_CCM_COSR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void _clk_cko1_disable(struct clk *clk)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOEN;
|
|
__raw_writel(reg, MXC_CCM_COSR);
|
|
}
|
|
|
|
static struct clk cko1_clk = {
|
|
.name = "cko1_clk",
|
|
.get_rate = _clk_cko1_get_rate,
|
|
.set_rate = _clk_cko1_set_rate,
|
|
.round_rate = _clk_cko1_round_rate,
|
|
.set_parent = _clk_cko1_set_parent,
|
|
.enable = _clk_cko1_enable,
|
|
.disable = _clk_cko1_disable,
|
|
};
|
|
|
|
static struct clk *mxc_clks[] = {
|
|
&ckih_clk,
|
|
&ckil_clk,
|
|
&mcu_pll_clk,
|
|
&usb_pll_clk,
|
|
&serial_pll_clk,
|
|
&mcu_main_clk,
|
|
&ahb_clk,
|
|
&per_clk,
|
|
&perclk_clk,
|
|
&cko1_clk,
|
|
&emi_clk,
|
|
&cspi_clk[0],
|
|
&cspi_clk[1],
|
|
&cspi_clk[2],
|
|
&ipg_clk,
|
|
&gpt_clk,
|
|
&pwm_clk,
|
|
&wdog_clk,
|
|
&rtc_clk,
|
|
&epit_clk[0],
|
|
&epit_clk[1],
|
|
&nfc_clk,
|
|
&ipu_clk,
|
|
&kpp_clk,
|
|
&usb_clk[0],
|
|
&usb_clk[1],
|
|
&csi_clk,
|
|
&uart_clk[0],
|
|
&uart_clk[1],
|
|
&uart_clk[2],
|
|
&uart_clk[3],
|
|
&uart_clk[4],
|
|
&i2c_clk[0],
|
|
&i2c_clk[1],
|
|
&i2c_clk[2],
|
|
&owire_clk,
|
|
&sdhc_clk[0],
|
|
&sdhc_clk[1],
|
|
&ssi_clk[0],
|
|
&ssi_clk[1],
|
|
&firi_clk,
|
|
&ata_clk,
|
|
&rtic_clk,
|
|
&rng_clk,
|
|
&sdma_clk[0],
|
|
&sdma_clk[1],
|
|
&mstick_clk[0],
|
|
&mstick_clk[1],
|
|
&scc_clk,
|
|
&iim_clk,
|
|
};
|
|
|
|
int __init mxc_clocks_init(unsigned long fref)
|
|
{
|
|
u32 reg;
|
|
struct clk **clkp;
|
|
|
|
ckih_rate = fref;
|
|
|
|
for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++)
|
|
clk_register(*clkp);
|
|
|
|
if (cpu_is_mx31()) {
|
|
clk_register(&mpeg4_clk);
|
|
clk_register(&mbx_clk);
|
|
} else {
|
|
clk_register(&vpu_clk);
|
|
clk_register(&vl2cc_clk);
|
|
}
|
|
|
|
/* Turn off all possible clocks */
|
|
__raw_writel(MXC_CCM_CGR0_GPT_MASK, MXC_CCM_CGR0);
|
|
__raw_writel(0, MXC_CCM_CGR1);
|
|
|
|
__raw_writel(MXC_CCM_CGR2_EMI_MASK |
|
|
MXC_CCM_CGR2_IPMUX1_MASK |
|
|
MXC_CCM_CGR2_IPMUX2_MASK |
|
|
MXC_CCM_CGR2_MXCCLKENSEL_MASK | /* for MX32 */
|
|
MXC_CCM_CGR2_CHIKCAMPEN_MASK | /* for MX32 */
|
|
MXC_CCM_CGR2_OVRVPUBUSY_MASK | /* for MX32 */
|
|
1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for
|
|
MX32, but still required to be set */
|
|
MXC_CCM_CGR2);
|
|
|
|
clk_disable(&cko1_clk);
|
|
clk_disable(&usb_pll_clk);
|
|
|
|
pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk));
|
|
|
|
clk_enable(&gpt_clk);
|
|
clk_enable(&emi_clk);
|
|
clk_enable(&iim_clk);
|
|
|
|
clk_enable(&serial_pll_clk);
|
|
|
|
if (mx31_revision() >= CHIP_REV_2_0) {
|
|
reg = __raw_readl(MXC_CCM_PMCR1);
|
|
/* No PLL restart on DVFS switch; enable auto EMI handshake */
|
|
reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;
|
|
__raw_writel(reg, MXC_CCM_PMCR1);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|