312 lines
7.3 KiB
C
312 lines
7.3 KiB
C
/***************************************************************************/
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/*
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* linux/arch/m68knommu/platform/520x/config.c
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*
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* Copyright (C) 2005, Freescale (www.freescale.com)
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* Copyright (C) 2005, Intec Automation (mike@steroidmicros.com)
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* Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com)
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* Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
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*/
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/***************************************************************************/
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/spi/spi.h>
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#include <linux/gpio.h>
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#include <asm/machdep.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/mcfuart.h>
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#include <asm/mcfqspi.h>
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/***************************************************************************/
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static struct mcf_platform_uart m520x_uart_platform[] = {
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{
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.mapbase = MCF_MBAR + MCFUART_BASE1,
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.irq = MCFINT_VECBASE + MCFINT_UART0,
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},
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{
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.mapbase = MCF_MBAR + MCFUART_BASE2,
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.irq = MCFINT_VECBASE + MCFINT_UART1,
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},
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{
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.mapbase = MCF_MBAR + MCFUART_BASE3,
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.irq = MCFINT_VECBASE + MCFINT_UART2,
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},
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{ },
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};
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static struct platform_device m520x_uart = {
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.name = "mcfuart",
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.id = 0,
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.dev.platform_data = m520x_uart_platform,
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};
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static struct resource m520x_fec_resources[] = {
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{
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.start = MCF_MBAR + 0x30000,
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.end = MCF_MBAR + 0x30000 + 0x7ff,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = 64 + 36,
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.end = 64 + 36,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = 64 + 40,
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.end = 64 + 40,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = 64 + 42,
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.end = 64 + 42,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device m520x_fec = {
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.name = "fec",
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.id = 0,
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.num_resources = ARRAY_SIZE(m520x_fec_resources),
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.resource = m520x_fec_resources,
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};
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#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
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static struct resource m520x_qspi_resources[] = {
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{
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.start = MCFQSPI_IOBASE,
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.end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MCFINT_VECBASE + MCFINT_QSPI,
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.end = MCFINT_VECBASE + MCFINT_QSPI,
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.flags = IORESOURCE_IRQ,
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},
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};
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#define MCFQSPI_CS0 62
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#define MCFQSPI_CS1 63
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#define MCFQSPI_CS2 44
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static int m520x_cs_setup(struct mcfqspi_cs_control *cs_control)
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{
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int status;
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status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
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if (status) {
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pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
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goto fail0;
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}
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status = gpio_direction_output(MCFQSPI_CS0, 1);
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if (status) {
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pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
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goto fail1;
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}
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status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
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if (status) {
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pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
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goto fail1;
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}
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status = gpio_direction_output(MCFQSPI_CS1, 1);
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if (status) {
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pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
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goto fail2;
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}
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status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
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if (status) {
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pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
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goto fail2;
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}
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status = gpio_direction_output(MCFQSPI_CS2, 1);
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if (status) {
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pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
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goto fail3;
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}
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return 0;
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fail3:
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gpio_free(MCFQSPI_CS2);
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fail2:
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gpio_free(MCFQSPI_CS1);
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fail1:
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gpio_free(MCFQSPI_CS0);
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fail0:
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return status;
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}
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static void m520x_cs_teardown(struct mcfqspi_cs_control *cs_control)
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{
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gpio_free(MCFQSPI_CS2);
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gpio_free(MCFQSPI_CS1);
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gpio_free(MCFQSPI_CS0);
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}
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static void m520x_cs_select(struct mcfqspi_cs_control *cs_control,
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u8 chip_select, bool cs_high)
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{
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switch (chip_select) {
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case 0:
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gpio_set_value(MCFQSPI_CS0, cs_high);
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break;
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case 1:
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gpio_set_value(MCFQSPI_CS1, cs_high);
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break;
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case 2:
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gpio_set_value(MCFQSPI_CS2, cs_high);
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break;
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}
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}
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static void m520x_cs_deselect(struct mcfqspi_cs_control *cs_control,
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u8 chip_select, bool cs_high)
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{
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switch (chip_select) {
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case 0:
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gpio_set_value(MCFQSPI_CS0, !cs_high);
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break;
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case 1:
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gpio_set_value(MCFQSPI_CS1, !cs_high);
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break;
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case 2:
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gpio_set_value(MCFQSPI_CS2, !cs_high);
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break;
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}
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}
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static struct mcfqspi_cs_control m520x_cs_control = {
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.setup = m520x_cs_setup,
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.teardown = m520x_cs_teardown,
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.select = m520x_cs_select,
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.deselect = m520x_cs_deselect,
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};
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static struct mcfqspi_platform_data m520x_qspi_data = {
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.bus_num = 0,
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.num_chipselect = 3,
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.cs_control = &m520x_cs_control,
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};
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static struct platform_device m520x_qspi = {
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.name = "mcfqspi",
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.id = 0,
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.num_resources = ARRAY_SIZE(m520x_qspi_resources),
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.resource = m520x_qspi_resources,
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.dev.platform_data = &m520x_qspi_data,
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};
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static void __init m520x_qspi_init(void)
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{
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u16 par;
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/* setup Port QS for QSPI with gpio CS control */
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writeb(0x3f, MCF_IPSBAR + MCF_GPIO_PAR_QSPI);
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/* make U1CTS and U2RTS gpio for cs_control */
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par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
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par &= 0x00ff;
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writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART);
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}
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#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
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static struct platform_device *m520x_devices[] __initdata = {
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&m520x_uart,
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&m520x_fec,
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#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
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&m520x_qspi,
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#endif
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};
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/***************************************************************************/
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static void __init m520x_uart_init_line(int line, int irq)
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{
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u16 par;
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u8 par2;
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switch (line) {
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case 0:
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par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
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par |= MCF_GPIO_PAR_UART_PAR_UTXD0 |
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MCF_GPIO_PAR_UART_PAR_URXD0;
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writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART);
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break;
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case 1:
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par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
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par |= MCF_GPIO_PAR_UART_PAR_UTXD1 |
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MCF_GPIO_PAR_UART_PAR_URXD1;
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writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART);
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break;
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case 2:
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par2 = readb(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C);
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par2 &= ~0x0F;
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par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
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MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
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writeb(par2, MCF_IPSBAR + MCF_GPIO_PAR_FECI2C);
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break;
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}
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}
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static void __init m520x_uarts_init(void)
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{
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const int nrlines = ARRAY_SIZE(m520x_uart_platform);
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int line;
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for (line = 0; (line < nrlines); line++)
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m520x_uart_init_line(line, m520x_uart_platform[line].irq);
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}
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/***************************************************************************/
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static void __init m520x_fec_init(void)
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{
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u8 v;
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/* Set multi-function pins to ethernet mode */
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v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FEC);
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writeb(v | 0xf0, MCF_IPSBAR + MCF_GPIO_PAR_FEC);
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v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C);
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writeb(v | 0x0f, MCF_IPSBAR + MCF_GPIO_PAR_FECI2C);
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}
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/***************************************************************************/
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static void m520x_cpu_reset(void)
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{
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local_irq_disable();
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__raw_writeb(MCF_RCR_SWRESET, MCF_RCR);
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}
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/***************************************************************************/
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void __init config_BSP(char *commandp, int size)
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{
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mach_reset = m520x_cpu_reset;
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m520x_uarts_init();
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m520x_fec_init();
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#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
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m520x_qspi_init();
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#endif
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}
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/***************************************************************************/
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static int __init init_BSP(void)
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{
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platform_add_devices(m520x_devices, ARRAY_SIZE(m520x_devices));
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return 0;
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}
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arch_initcall(init_BSP);
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/***************************************************************************/
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