193 lines
5.4 KiB
ArmAsm
193 lines
5.4 KiB
ArmAsm
/* MN10300 CPU core caching routines
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#include <linux/sys.h>
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#include <linux/linkage.h>
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#include <asm/smp.h>
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#include <asm/page.h>
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#include <asm/cache.h>
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.am33_2
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.globl mn10300_dcache_flush
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.globl mn10300_dcache_flush_page
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.globl mn10300_dcache_flush_range
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.globl mn10300_dcache_flush_range2
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.globl mn10300_dcache_flush_inv
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.globl mn10300_dcache_flush_inv_page
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.globl mn10300_dcache_flush_inv_range
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.globl mn10300_dcache_flush_inv_range2
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###############################################################################
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#
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# void mn10300_dcache_flush(void)
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# Flush the entire data cache back to RAM
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#
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###############################################################################
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ALIGN
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mn10300_dcache_flush:
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movhu (CHCTR),d0
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btst CHCTR_DCEN,d0
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beq mn10300_dcache_flush_end
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# read the addresses tagged in the cache's tag RAM and attempt to flush
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# those addresses specifically
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# - we rely on the hardware to filter out invalid tag entry addresses
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mov DCACHE_TAG(0,0),a0 # dcache tag RAM access address
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mov DCACHE_PURGE(0,0),a1 # dcache purge request address
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mov L1_CACHE_NWAYS*L1_CACHE_NENTRIES,d1 # total number of entries
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mn10300_dcache_flush_loop:
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mov (a0),d0
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and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d0
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or L1_CACHE_TAG_VALID,d0 # retain valid entries in the
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# cache
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mov d0,(a1) # conditional purge
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mn10300_dcache_flush_skip:
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add L1_CACHE_BYTES,a0
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add L1_CACHE_BYTES,a1
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add -1,d1
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bne mn10300_dcache_flush_loop
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mn10300_dcache_flush_end:
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ret [],0
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###############################################################################
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#
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# void mn10300_dcache_flush_page(unsigned start)
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# void mn10300_dcache_flush_range(unsigned start, unsigned end)
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# void mn10300_dcache_flush_range2(unsigned start, unsigned size)
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# Flush a range of addresses on a page in the dcache
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#
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###############################################################################
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ALIGN
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mn10300_dcache_flush_page:
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mov PAGE_SIZE,d1
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mn10300_dcache_flush_range2:
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add d0,d1
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mn10300_dcache_flush_range:
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movm [d2,d3],(sp)
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movhu (CHCTR),d2
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btst CHCTR_DCEN,d2
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beq mn10300_dcache_flush_range_end
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# round start addr down
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and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d0
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mov d0,a1
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add L1_CACHE_BYTES,d1 # round end addr up
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and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d1
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# write a request to flush all instances of an address from the cache
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mov DCACHE_PURGE(0,0),a0
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mov a1,d0
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and L1_CACHE_TAG_ENTRY,d0
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add d0,a0 # starting dcache purge control
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# reg address
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sub a1,d1
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lsr L1_CACHE_SHIFT,d1 # total number of entries to
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# examine
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or L1_CACHE_TAG_VALID,a1 # retain valid entries in the
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# cache
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mn10300_dcache_flush_range_loop:
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mov a1,(L1_CACHE_WAYDISP*0,a0) # conditionally purge this line
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# all ways
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add L1_CACHE_BYTES,a0
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add L1_CACHE_BYTES,a1
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and ~L1_CACHE_WAYDISP,a0 # make sure way stay on way 0
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add -1,d1
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bne mn10300_dcache_flush_range_loop
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mn10300_dcache_flush_range_end:
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ret [d2,d3],8
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###############################################################################
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#
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# void mn10300_dcache_flush_inv(void)
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# Flush the entire data cache and invalidate all entries
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#
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###############################################################################
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ALIGN
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mn10300_dcache_flush_inv:
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movhu (CHCTR),d0
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btst CHCTR_DCEN,d0
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beq mn10300_dcache_flush_inv_end
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# hit each line in the dcache with an unconditional purge
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mov DCACHE_PURGE(0,0),a1 # dcache purge request address
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mov L1_CACHE_NWAYS*L1_CACHE_NENTRIES,d1 # total number of entries
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mn10300_dcache_flush_inv_loop:
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mov (a1),d0 # unconditional purge
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add L1_CACHE_BYTES,a1
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add -1,d1
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bne mn10300_dcache_flush_inv_loop
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mn10300_dcache_flush_inv_end:
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ret [],0
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###############################################################################
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#
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# void mn10300_dcache_flush_inv_page(unsigned start)
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# void mn10300_dcache_flush_inv_range(unsigned start, unsigned end)
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# void mn10300_dcache_flush_inv_range2(unsigned start, unsigned size)
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# Flush and invalidate a range of addresses on a page in the dcache
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#
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###############################################################################
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ALIGN
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mn10300_dcache_flush_inv_page:
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mov PAGE_SIZE,d1
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mn10300_dcache_flush_inv_range2:
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add d0,d1
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mn10300_dcache_flush_inv_range:
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movm [d2,d3],(sp)
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movhu (CHCTR),d2
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btst CHCTR_DCEN,d2
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beq mn10300_dcache_flush_inv_range_end
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and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d0 # round start
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# addr down
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mov d0,a1
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add L1_CACHE_BYTES,d1 # round end addr up
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and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d1
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# write a request to flush and invalidate all instances of an address
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# from the cache
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mov DCACHE_PURGE(0,0),a0
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mov a1,d0
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and L1_CACHE_TAG_ENTRY,d0
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add d0,a0 # starting dcache purge control
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# reg address
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sub a1,d1
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lsr L1_CACHE_SHIFT,d1 # total number of entries to
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# examine
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mn10300_dcache_flush_inv_range_loop:
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mov a1,(L1_CACHE_WAYDISP*0,a0) # conditionally purge this line
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# in all ways
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add L1_CACHE_BYTES,a0
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add L1_CACHE_BYTES,a1
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and ~L1_CACHE_WAYDISP,a0 # make sure way stay on way 0
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add -1,d1
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bne mn10300_dcache_flush_inv_range_loop
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mn10300_dcache_flush_inv_range_end:
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ret [d2,d3],8
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