103 lines
2.9 KiB
C
103 lines
2.9 KiB
C
/*
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* Modifications by Matt Porter (mporter@mvista.com) to support
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* PPC44x Book E processors.
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*
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* This file contains the routines for initializing the MMU
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* on the 4xx series of chips.
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* -- paulus
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*
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* Derived from arch/ppc/mm/init.c:
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
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* and Cort Dougan (PReP) (cort@cs.nmt.edu)
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* Copyright (C) 1996 Paul Mackerras
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*
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* Derived from "arch/i386/mm/init.c"
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* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/init.h>
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#include <asm/mmu.h>
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#include <asm/system.h>
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#include <asm/page.h>
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#include <asm/cacheflush.h>
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#include "mmu_decl.h"
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/* Used by the 44x TLB replacement exception handler.
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* Just needed it declared someplace.
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*/
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unsigned int tlb_44x_index; /* = 0 */
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unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
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int icache_44x_need_flush;
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static void __init ppc44x_update_tlb_hwater(void)
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{
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extern unsigned int tlb_44x_patch_hwater_D[];
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extern unsigned int tlb_44x_patch_hwater_I[];
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/* The TLB miss handlers hard codes the watermark in a cmpli
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* instruction to improve performances rather than loading it
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* from the global variable. Thus, we patch the instructions
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* in the 2 TLB miss handlers when updating the value
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*/
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tlb_44x_patch_hwater_D[0] = (tlb_44x_patch_hwater_D[0] & 0xffff0000) |
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tlb_44x_hwater;
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flush_icache_range((unsigned long)&tlb_44x_patch_hwater_D[0],
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(unsigned long)&tlb_44x_patch_hwater_D[1]);
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tlb_44x_patch_hwater_I[0] = (tlb_44x_patch_hwater_I[0] & 0xffff0000) |
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tlb_44x_hwater;
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flush_icache_range((unsigned long)&tlb_44x_patch_hwater_I[0],
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(unsigned long)&tlb_44x_patch_hwater_I[1]);
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}
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/*
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* "Pins" a 256MB TLB entry in AS0 for kernel lowmem
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*/
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static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
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{
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unsigned int entry = tlb_44x_hwater--;
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ppc44x_update_tlb_hwater();
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__asm__ __volatile__(
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"tlbwe %2,%3,%4\n"
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"tlbwe %1,%3,%5\n"
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"tlbwe %0,%3,%6\n"
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:
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: "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
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"r" (phys),
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"r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M),
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"r" (entry),
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"i" (PPC44x_TLB_PAGEID),
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"i" (PPC44x_TLB_XLAT),
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"i" (PPC44x_TLB_ATTRIB));
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}
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void __init MMU_init_hw(void)
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{
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ppc44x_update_tlb_hwater();
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flush_instruction_cache();
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}
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unsigned long __init mmu_mapin_ram(unsigned long top)
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{
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unsigned long addr;
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/* Pin in enough TLBs to cover any lowmem not covered by the
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* initial 256M mapping established in head_44x.S */
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for (addr = PPC_PIN_SIZE; addr < lowmem_end_addr;
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addr += PPC_PIN_SIZE)
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ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
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return total_lowmem;
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}
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