194 lines
6.6 KiB
C
194 lines
6.6 KiB
C
/*
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* include/asm-ppc/mpc85xx.h
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*
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* MPC85xx definitions
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*
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* Maintainer: Kumar Gala <kumar.gala@freescale.com>
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*
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* Copyright 2004 Freescale Semiconductor, Inc
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifdef __KERNEL__
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#ifndef __ASM_MPC85xx_H__
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#define __ASM_MPC85xx_H__
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#include <linux/config.h>
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#include <asm/mmu.h>
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#ifdef CONFIG_85xx
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#ifdef CONFIG_MPC8540_ADS
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#include <platforms/85xx/mpc8540_ads.h>
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#endif
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#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
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#include <platforms/85xx/mpc8555_cds.h>
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#endif
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#ifdef CONFIG_MPC8560_ADS
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#include <platforms/85xx/mpc8560_ads.h>
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#endif
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#ifdef CONFIG_SBC8560
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#include <platforms/85xx/sbc8560.h>
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#endif
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#ifdef CONFIG_STX_GP3
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#include <platforms/85xx/stx_gp3.h>
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#endif
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#define _IO_BASE isa_io_base
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#define _ISA_MEM_BASE isa_mem_base
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#ifdef CONFIG_PCI
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#define PCI_DRAM_OFFSET pci_dram_offset
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#else
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#define PCI_DRAM_OFFSET 0
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#endif
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/*
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* The "residual" board information structure the boot loader passes
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* into the kernel.
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*/
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extern unsigned char __res[];
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/* Offset from CCSRBAR */
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#define MPC85xx_CPM_OFFSET (0x80000)
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#define MPC85xx_CPM_SIZE (0x40000)
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#define MPC85xx_DMA_OFFSET (0x21000)
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#define MPC85xx_DMA_SIZE (0x01000)
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#define MPC85xx_DMA0_OFFSET (0x21100)
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#define MPC85xx_DMA0_SIZE (0x00080)
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#define MPC85xx_DMA1_OFFSET (0x21180)
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#define MPC85xx_DMA1_SIZE (0x00080)
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#define MPC85xx_DMA2_OFFSET (0x21200)
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#define MPC85xx_DMA2_SIZE (0x00080)
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#define MPC85xx_DMA3_OFFSET (0x21280)
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#define MPC85xx_DMA3_SIZE (0x00080)
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#define MPC85xx_ENET1_OFFSET (0x24000)
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#define MPC85xx_ENET1_SIZE (0x01000)
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#define MPC85xx_MIIM_OFFSET (0x24520)
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#define MPC85xx_MIIM_SIZE (0x00018)
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#define MPC85xx_ENET2_OFFSET (0x25000)
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#define MPC85xx_ENET2_SIZE (0x01000)
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#define MPC85xx_ENET3_OFFSET (0x26000)
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#define MPC85xx_ENET3_SIZE (0x01000)
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#define MPC85xx_GUTS_OFFSET (0xe0000)
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#define MPC85xx_GUTS_SIZE (0x01000)
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#define MPC85xx_IIC1_OFFSET (0x03000)
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#define MPC85xx_IIC1_SIZE (0x00100)
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#define MPC85xx_OPENPIC_OFFSET (0x40000)
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#define MPC85xx_OPENPIC_SIZE (0x40000)
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#define MPC85xx_PCI1_OFFSET (0x08000)
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#define MPC85xx_PCI1_SIZE (0x01000)
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#define MPC85xx_PCI2_OFFSET (0x09000)
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#define MPC85xx_PCI2_SIZE (0x01000)
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#define MPC85xx_PERFMON_OFFSET (0xe1000)
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#define MPC85xx_PERFMON_SIZE (0x01000)
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#define MPC85xx_SEC2_OFFSET (0x30000)
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#define MPC85xx_SEC2_SIZE (0x10000)
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#define MPC85xx_UART0_OFFSET (0x04500)
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#define MPC85xx_UART0_SIZE (0x00100)
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#define MPC85xx_UART1_OFFSET (0x04600)
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#define MPC85xx_UART1_SIZE (0x00100)
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#define MPC85xx_CCSRBAR_SIZE (1024*1024)
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/* Let modules/drivers get at CCSRBAR */
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extern phys_addr_t get_ccsrbar(void);
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#ifdef MODULE
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#define CCSRBAR get_ccsrbar()
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#else
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#define CCSRBAR BOARD_CCSRBAR
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#endif
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enum ppc_sys_devices {
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MPC85xx_TSEC1,
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MPC85xx_TSEC2,
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MPC85xx_FEC,
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MPC85xx_IIC1,
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MPC85xx_DMA0,
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MPC85xx_DMA1,
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MPC85xx_DMA2,
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MPC85xx_DMA3,
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MPC85xx_DUART,
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MPC85xx_PERFMON,
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MPC85xx_SEC2,
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MPC85xx_CPM_SPI,
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MPC85xx_CPM_I2C,
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MPC85xx_CPM_USB,
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MPC85xx_CPM_SCC1,
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MPC85xx_CPM_SCC2,
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MPC85xx_CPM_SCC3,
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MPC85xx_CPM_SCC4,
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MPC85xx_CPM_FCC1,
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MPC85xx_CPM_FCC2,
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MPC85xx_CPM_FCC3,
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MPC85xx_CPM_MCC1,
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MPC85xx_CPM_MCC2,
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MPC85xx_CPM_SMC1,
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MPC85xx_CPM_SMC2,
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MPC85xx_eTSEC1,
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MPC85xx_eTSEC2,
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MPC85xx_eTSEC3,
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MPC85xx_eTSEC4,
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MPC85xx_IIC2,
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MPC85xx_MDIO,
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};
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/* Internal interrupts are all Level Sensitive, and Positive Polarity */
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#define MPC85XX_INTERNAL_IRQ_SENSES \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46 */ \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE) /* Internal 47 */
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#endif /* CONFIG_85xx */
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#endif /* __ASM_MPC85xx_H__ */
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#endif /* __KERNEL__ */
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