63 lines
1.5 KiB
C
63 lines
1.5 KiB
C
/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h
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*
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C24xx - common pll registers and code
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*/
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#define S3C24XX_PLLCON_MDIVSHIFT 12
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#define S3C24XX_PLLCON_PDIVSHIFT 4
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#define S3C24XX_PLLCON_SDIVSHIFT 0
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#define S3C24XX_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1)
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#define S3C24XX_PLLCON_PDIVMASK ((1<<5)-1)
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#define S3C24XX_PLLCON_SDIVMASK 3
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#include <asm/div64.h>
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static inline unsigned int
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s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk)
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{
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unsigned int mdiv, pdiv, sdiv;
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uint64_t fvco;
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mdiv = pllval >> S3C24XX_PLLCON_MDIVSHIFT;
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pdiv = pllval >> S3C24XX_PLLCON_PDIVSHIFT;
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sdiv = pllval >> S3C24XX_PLLCON_SDIVSHIFT;
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mdiv &= S3C24XX_PLLCON_MDIVMASK;
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pdiv &= S3C24XX_PLLCON_PDIVMASK;
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sdiv &= S3C24XX_PLLCON_SDIVMASK;
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fvco = (uint64_t)baseclk * (mdiv + 8);
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do_div(fvco, (pdiv + 2) << sdiv);
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return (unsigned int)fvco;
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}
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#define S3C2416_PLL_M_SHIFT (14)
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#define S3C2416_PLL_P_SHIFT (5)
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#define S3C2416_PLL_S_MASK (7)
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#define S3C2416_PLL_M_MASK ((1 << 10) - 1)
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#define S3C2416_PLL_P_MASK (63)
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static inline unsigned int
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s3c2416_get_pll(unsigned int pllval, unsigned int baseclk)
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{
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unsigned int m, p, s;
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uint64_t fvco;
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m = pllval >> S3C2416_PLL_M_SHIFT;
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p = pllval >> S3C2416_PLL_P_SHIFT;
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s = pllval & S3C2416_PLL_S_MASK;
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m &= S3C2416_PLL_M_MASK;
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p &= S3C2416_PLL_P_MASK;
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fvco = (uint64_t)baseclk * m;
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do_div(fvco, (p << s));
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return (unsigned int)fvco;
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}
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