79 lines
1.9 KiB
C
79 lines
1.9 KiB
C
/*
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* AVR32 OCD Registers
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*
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* Copyright (C) 2004-2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_AVR32_OCD_H
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#define __ASM_AVR32_OCD_H
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/* Debug Registers */
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#define DBGREG_DID 0
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#define DBGREG_DC 8
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#define DBGREG_DS 16
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#define DBGREG_RWCS 28
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#define DBGREG_RWA 36
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#define DBGREG_RWD 40
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#define DBGREG_WT 44
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#define DBGREG_DTC 52
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#define DBGREG_DTSA0 56
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#define DBGREG_DTSA1 60
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#define DBGREG_DTEA0 72
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#define DBGREG_DTEA1 76
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#define DBGREG_BWC0A 88
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#define DBGREG_BWC0B 92
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#define DBGREG_BWC1A 96
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#define DBGREG_BWC1B 100
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#define DBGREG_BWC2A 104
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#define DBGREG_BWC2B 108
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#define DBGREG_BWC3A 112
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#define DBGREG_BWC3B 116
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#define DBGREG_BWA0A 120
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#define DBGREG_BWA0B 124
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#define DBGREG_BWA1A 128
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#define DBGREG_BWA1B 132
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#define DBGREG_BWA2A 136
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#define DBGREG_BWA2B 140
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#define DBGREG_BWA3A 144
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#define DBGREG_BWA3B 148
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#define DBGREG_BWD3A 153
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#define DBGREG_BWD3B 156
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#define DBGREG_PID 284
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#define SABAH_OCD 0x01
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#define SABAH_ICACHE 0x02
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#define SABAH_MEM_CACHED 0x04
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#define SABAH_MEM_UNCACHED 0x05
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/* Fields in the Development Control register */
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#define DC_SS_BIT 8
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#define DC_SS (1 << DC_SS_BIT)
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#define DC_DBE (1 << 13)
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#define DC_RID (1 << 27)
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#define DC_ORP (1 << 28)
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#define DC_MM (1 << 29)
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#define DC_RES (1 << 30)
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/* Fields in the Development Status register */
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#define DS_SSS (1 << 0)
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#define DS_SWB (1 << 1)
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#define DS_HWB (1 << 2)
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#define DS_BP_SHIFT 8
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#define DS_BP_MASK (0xff << DS_BP_SHIFT)
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#define __mfdr(addr) \
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({ \
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register unsigned long value; \
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asm volatile("mfdr %0, %1" : "=r"(value) : "i"(addr)); \
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value; \
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})
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#define __mtdr(addr, value) \
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asm volatile("mtdr %0, %1" : : "i"(addr), "r"(value))
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#endif /* __ASM_AVR32_OCD_H */
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