159 lines
4.0 KiB
C
159 lines
4.0 KiB
C
/*
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* PCIEHPRM NONACPI: PHP Resource Manager for Non-ACPI/Legacy platform
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*
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* Copyright (C) 1995,2001 Compaq Computer Corporation
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* Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
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* Copyright (C) 2001 IBM Corp.
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* Copyright (C) 2003-2004 Intel Corporation
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*
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
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*
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <asm/uaccess.h>
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#include "pciehp.h"
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#include "pciehprm.h"
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#include "pciehprm_nonacpi.h"
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void pciehprm_cleanup(void)
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{
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return;
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}
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int pciehprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busnum, u8 devnum)
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{
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*sun = (u8) (ctrl->first_slot);
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return 0;
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}
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int pciehprm_set_hpp(
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struct controller *ctrl,
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struct pci_func *func,
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u8 card_type)
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{
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u32 rc;
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u8 temp_byte;
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struct pci_bus lpci_bus, *pci_bus;
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unsigned int devfn;
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memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
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pci_bus = &lpci_bus;
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pci_bus->number = func->bus;
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devfn = PCI_DEVFN(func->device, func->function);
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temp_byte = 0x40; /* hard coded value for LT */
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if (card_type == PCI_HEADER_TYPE_BRIDGE) {
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/* set subordinate Latency Timer */
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rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_SEC_LATENCY_TIMER, temp_byte);
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if (rc) {
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dbg("%s: set secondary LT error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__,
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func->bus, func->device, func->function);
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return rc;
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}
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}
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/* set base Latency Timer */
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rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_LATENCY_TIMER, temp_byte);
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if (rc) {
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dbg("%s: set LT error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus, func->device, func->function);
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return rc;
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}
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/* set Cache Line size */
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temp_byte = 0x08; /* hard coded value for CLS */
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rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_CACHE_LINE_SIZE, temp_byte);
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if (rc) {
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dbg("%s: set CLS error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus, func->device, func->function);
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}
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/* set enable_perr */
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/* set enable_serr */
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return rc;
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}
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void pciehprm_enable_card(
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struct controller *ctrl,
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struct pci_func *func,
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u8 card_type)
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{
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u16 command, bcommand;
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struct pci_bus lpci_bus, *pci_bus;
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unsigned int devfn;
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int rc;
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memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
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pci_bus = &lpci_bus;
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pci_bus->number = func->bus;
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devfn = PCI_DEVFN(func->device, func->function);
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rc = pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &command);
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command |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR
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| PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
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| PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
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rc = pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
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if (card_type == PCI_HEADER_TYPE_BRIDGE) {
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rc = pci_bus_read_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, &bcommand);
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bcommand |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR
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| PCI_BRIDGE_CTL_NO_ISA;
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rc = pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, bcommand);
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}
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}
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static int legacy_pciehprm_init_pci(void)
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{
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return 0;
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}
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int pciehprm_init(enum php_ctlr_type ctrl_type)
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{
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int retval;
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switch (ctrl_type) {
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case PCI:
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retval = legacy_pciehprm_init_pci();
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break;
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default:
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retval = -ENODEV;
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break;
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}
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return retval;
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}
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