386 lines
15 KiB
XML
386 lines
15 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE book PUBLIC "-//OASIS//DTD DocBook XML V4.1.2//EN"
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"http://www.oasis-open.org/docbook/xml/4.1.2/docbookx.dtd" []>
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<book id="Z85230Guide">
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<bookinfo>
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<title>Z8530 Programming Guide</title>
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<authorgroup>
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<author>
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<firstname>Alan</firstname>
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<surname>Cox</surname>
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<affiliation>
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<address>
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<email>alan@redhat.com</email>
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</address>
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</affiliation>
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</author>
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</authorgroup>
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<copyright>
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<year>2000</year>
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<holder>Alan Cox</holder>
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</copyright>
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<legalnotice>
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<para>
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This documentation is free software; you can redistribute
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it and/or modify it under the terms of the GNU General Public
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License as published by the Free Software Foundation; either
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version 2 of the License, or (at your option) any later
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version.
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</para>
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<para>
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This program is distributed in the hope that it will be
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useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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See the GNU General Public License for more details.
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</para>
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<para>
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You should have received a copy of the GNU General Public
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License along with this program; if not, write to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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MA 02111-1307 USA
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</para>
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<para>
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For more details see the file COPYING in the source
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distribution of Linux.
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</para>
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</legalnotice>
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</bookinfo>
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<toc></toc>
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<chapter id="intro">
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<title>Introduction</title>
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<para>
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The Z85x30 family synchronous/asynchronous controller chips are
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used on a large number of cheap network interface cards. The
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kernel provides a core interface layer that is designed to make
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it easy to provide WAN services using this chip.
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</para>
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<para>
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The current driver only support synchronous operation. Merging the
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asynchronous driver support into this code to allow any Z85x30
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device to be used as both a tty interface and as a synchronous
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controller is a project for Linux post the 2.4 release
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</para>
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<para>
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The support code handles most common card configurations and
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supports running both Cisco HDLC and Synchronous PPP. With extra
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glue the frame relay and X.25 protocols can also be used with this
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driver.
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</para>
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</chapter>
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<chapter id="Driver_Modes">
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<title>Driver Modes</title>
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<para>
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The Z85230 driver layer can drive Z8530, Z85C30 and Z85230 devices
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in three different modes. Each mode can be applied to an individual
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channel on the chip (each chip has two channels).
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</para>
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<para>
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The PIO synchronous mode supports the most common Z8530 wiring. Here
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the chip is interface to the I/O and interrupt facilities of the
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host machine but not to the DMA subsystem. When running PIO the
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Z8530 has extremely tight timing requirements. Doing high speeds,
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even with a Z85230 will be tricky. Typically you should expect to
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achieve at best 9600 baud with a Z8C530 and 64Kbits with a Z85230.
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</para>
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<para>
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The DMA mode supports the chip when it is configured to use dual DMA
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channels on an ISA bus. The better cards tend to support this mode
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of operation for a single channel. With DMA running the Z85230 tops
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out when it starts to hit ISA DMA constraints at about 512Kbits. It
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is worth noting here that many PC machines hang or crash when the
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chip is driven fast enough to hold the ISA bus solid.
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</para>
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<para>
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Transmit DMA mode uses a single DMA channel. The DMA channel is used
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for transmission as the transmit FIFO is smaller than the receive
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FIFO. it gives better performance than pure PIO mode but is nowhere
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near as ideal as pure DMA mode.
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</para>
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</chapter>
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<chapter id="Using_the_Z85230_driver">
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<title>Using the Z85230 driver</title>
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<para>
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The Z85230 driver provides the back end interface to your board. To
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configure a Z8530 interface you need to detect the board and to
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identify its ports and interrupt resources. It is also your problem
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to verify the resources are available.
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</para>
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<para>
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Having identified the chip you need to fill in a struct z8530_dev,
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which describes each chip. This object must exist until you finally
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shutdown the board. Firstly zero the active field. This ensures
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nothing goes off without you intending it. The irq field should
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be set to the interrupt number of the chip. (Each chip has a single
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interrupt source rather than each channel). You are responsible
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for allocating the interrupt line. The interrupt handler should be
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set to <function>z8530_interrupt</function>. The device id should
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be set to the z8530_dev structure pointer. Whether the interrupt can
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be shared or not is board dependent, and up to you to initialise.
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</para>
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<para>
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The structure holds two channel structures.
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Initialise chanA.ctrlio and chanA.dataio with the address of the
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control and data ports. You can or this with Z8530_PORT_SLEEP to
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indicate your interface needs the 5uS delay for chip settling done
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in software. The PORT_SLEEP option is architecture specific. Other
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flags may become available on future platforms, eg for MMIO.
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Initialise the chanA.irqs to &z8530_nop to start the chip up
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as disabled and discarding interrupt events. This ensures that
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stray interrupts will be mopped up and not hang the bus. Set
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chanA.dev to point to the device structure itself. The
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private and name field you may use as you wish. The private field
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is unused by the Z85230 layer. The name is used for error reporting
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and it may thus make sense to make it match the network name.
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</para>
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<para>
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Repeat the same operation with the B channel if your chip has
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both channels wired to something useful. This isn't always the
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case. If it is not wired then the I/O values do not matter, but
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you must initialise chanB.dev.
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</para>
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<para>
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If your board has DMA facilities then initialise the txdma and
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rxdma fields for the relevant channels. You must also allocate the
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ISA DMA channels and do any necessary board level initialisation
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to configure them. The low level driver will do the Z8530 and
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DMA controller programming but not board specific magic.
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</para>
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<para>
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Having initialised the device you can then call
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<function>z8530_init</function>. This will probe the chip and
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reset it into a known state. An identification sequence is then
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run to identify the chip type. If the checks fail to pass the
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function returns a non zero error code. Typically this indicates
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that the port given is not valid. After this call the
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type field of the z8530_dev structure is initialised to either
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Z8530, Z85C30 or Z85230 according to the chip found.
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</para>
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<para>
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Once you have called z8530_init you can also make use of the utility
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function <function>z8530_describe</function>. This provides a
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consistent reporting format for the Z8530 devices, and allows all
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the drivers to provide consistent reporting.
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</para>
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</chapter>
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<chapter id="Attaching_Network_Interfaces">
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<title>Attaching Network Interfaces</title>
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<para>
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If you wish to use the network interface facilities of the driver,
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then you need to attach a network device to each channel that is
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present and in use. In addition to use the SyncPPP and Cisco HDLC
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you need to follow some additional plumbing rules. They may seem
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complex but a look at the example hostess_sv11 driver should
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reassure you.
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</para>
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<para>
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The network device used for each channel should be pointed to by
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the netdevice field of each channel. The dev-> priv field of the
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network device points to your private data - you will need to be
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able to find your ppp device from this. In addition to use the
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sync ppp layer the private data must start with a void * pointer
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to the syncppp structures.
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</para>
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<para>
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The way most drivers approach this particular problem is to
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create a structure holding the Z8530 device definition and
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put that and the syncppp pointer into the private field of
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the network device. The network device fields of the channels
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then point back to the network devices. The ppp_device can also
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be put in the private structure conveniently.
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</para>
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<para>
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If you wish to use the synchronous ppp then you need to attach
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the syncppp layer to the network device. You should do this before
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you register the network device. The
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<function>sppp_attach</function> requires that the first void *
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pointer in your private data is pointing to an empty struct
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ppp_device. The function fills in the initial data for the
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ppp/hdlc layer.
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</para>
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<para>
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Before you register your network device you will also need to
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provide suitable handlers for most of the network device callbacks.
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See the network device documentation for more details on this.
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</para>
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</chapter>
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<chapter id="Configuring_And_Activating_The_Port">
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<title>Configuring And Activating The Port</title>
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<para>
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The Z85230 driver provides helper functions and tables to load the
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port registers on the Z8530 chips. When programming the register
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settings for a channel be aware that the documentation recommends
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initialisation orders. Strange things happen when these are not
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followed.
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</para>
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<para>
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<function>z8530_channel_load</function> takes an array of
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pairs of initialisation values in an array of u8 type. The first
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value is the Z8530 register number. Add 16 to indicate the alternate
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register bank on the later chips. The array is terminated by a 255.
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</para>
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<para>
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The driver provides a pair of public tables. The
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z8530_hdlc_kilostream table is for the UK 'Kilostream' service and
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also happens to cover most other end host configurations. The
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z8530_hdlc_kilostream_85230 table is the same configuration using
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the enhancements of the 85230 chip. The configuration loaded is
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standard NRZ encoded synchronous data with HDLC bitstuffing. All
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of the timing is taken from the other end of the link.
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</para>
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<para>
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When writing your own tables be aware that the driver internally
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tracks register values. It may need to reload values. You should
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therefore be sure to set registers 1-7, 9-11, 14 and 15 in all
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configurations. Where the register settings depend on DMA selection
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the driver will update the bits itself when you open or close.
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Loading a new table with the interface open is not recommended.
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</para>
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<para>
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There are three standard configurations supported by the core
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code. In PIO mode the interface is programmed up to use
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interrupt driven PIO. This places high demands on the host processor
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to avoid latency. The driver is written to take account of latency
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issues but it cannot avoid latencies caused by other drivers,
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notably IDE in PIO mode. Because the drivers allocate buffers you
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must also prevent MTU changes while the port is open.
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</para>
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<para>
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Once the port is open it will call the rx_function of each channel
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whenever a completed packet arrived. This is invoked from
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interrupt context and passes you the channel and a network
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buffer (struct sk_buff) holding the data. The data includes
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the CRC bytes so most users will want to trim the last two
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bytes before processing the data. This function is very timing
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critical. When you wish to simply discard data the support
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code provides the function <function>z8530_null_rx</function>
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to discard the data.
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</para>
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<para>
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To active PIO mode sending and receiving the <function>
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z8530_sync_open</function> is called. This expects to be passed
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the network device and the channel. Typically this is called from
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your network device open callback. On a failure a non zero error
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status is returned. The <function>z8530_sync_close</function>
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function shuts down a PIO channel. This must be done before the
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channel is opened again and before the driver shuts down
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and unloads.
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</para>
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<para>
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The ideal mode of operation is dual channel DMA mode. Here the
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kernel driver will configure the board for DMA in both directions.
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The driver also handles ISA DMA issues such as controller
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programming and the memory range limit for you. This mode is
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activated by calling the <function>z8530_sync_dma_open</function>
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function. On failure a non zero error value is returned.
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Once this mode is activated it can be shut down by calling the
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<function>z8530_sync_dma_close</function>. You must call the close
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function matching the open mode you used.
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</para>
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<para>
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The final supported mode uses a single DMA channel to drive the
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transmit side. As the Z85C30 has a larger FIFO on the receive
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channel this tends to increase the maximum speed a little.
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This is activated by calling the <function>z8530_sync_txdma_open
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</function>. This returns a non zero error code on failure. The
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<function>z8530_sync_txdma_close</function> function closes down
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the Z8530 interface from this mode.
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</para>
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</chapter>
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<chapter id="Network_Layer_Functions">
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<title>Network Layer Functions</title>
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<para>
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The Z8530 layer provides functions to queue packets for
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transmission. The driver internally buffers the frame currently
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being transmitted and one further frame (in order to keep back
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to back transmission running). Any further buffering is up to
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the caller.
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</para>
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<para>
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The function <function>z8530_queue_xmit</function> takes a network
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buffer in sk_buff format and queues it for transmission. The
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caller must provide the entire packet with the exception of the
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bitstuffing and CRC. This is normally done by the caller via
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the syncppp interface layer. It returns 0 if the buffer has been
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queued and non zero values for queue full. If the function accepts
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the buffer it becomes property of the Z8530 layer and the caller
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should not free it.
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</para>
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<para>
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The function <function>z8530_get_stats</function> returns a pointer
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to an internally maintained per interface statistics block. This
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provides most of the interface code needed to implement the network
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layer get_stats callback.
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</para>
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</chapter>
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<chapter id="Porting_The_Z8530_Driver">
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<title>Porting The Z8530 Driver</title>
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<para>
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The Z8530 driver is written to be portable. In DMA mode it makes
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assumptions about the use of ISA DMA. These are probably warranted
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in most cases as the Z85230 in particular was designed to glue to PC
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type machines. The PIO mode makes no real assumptions.
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</para>
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<para>
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Should you need to retarget the Z8530 driver to another architecture
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the only code that should need changing are the port I/O functions.
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At the moment these assume PC I/O port accesses. This may not be
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appropriate for all platforms. Replacing
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<function>z8530_read_port</function> and <function>z8530_write_port
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</function> is intended to be all that is required to port this
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driver layer.
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</para>
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</chapter>
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<chapter id="bugs">
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<title>Known Bugs And Assumptions</title>
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<para>
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<variablelist>
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<varlistentry><term>Interrupt Locking</term>
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<listitem>
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<para>
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The locking in the driver is done via the global cli/sti lock. This
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makes for relatively poor SMP performance. Switching this to use a
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per device spin lock would probably materially improve performance.
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</para>
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</listitem></varlistentry>
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<varlistentry><term>Occasional Failures</term>
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<listitem>
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<para>
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We have reports of occasional failures when run for very long
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periods of time and the driver starts to receive junk frames. At
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the moment the cause of this is not clear.
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</para>
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</listitem></varlistentry>
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</variablelist>
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</para>
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</chapter>
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<chapter id="pubfunctions">
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<title>Public Functions Provided</title>
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!Edrivers/net/wan/z85230.c
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</chapter>
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<chapter id="intfunctions">
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<title>Internal Functions</title>
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!Idrivers/net/wan/z85230.c
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</chapter>
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</book>
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