213 lines
8.3 KiB
C
213 lines
8.3 KiB
C
#ifndef __mmu_defs_asm_h
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#define __mmu_defs_asm_h
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/*
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* This file is autogenerated from
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* file: ../../inst/mmu/doc/mmu_regs.r
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* id: mmu_regs.r,v 1.12 2004/05/06 13:48:45 mikaeln Exp
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* last modfied: Mon Apr 11 17:03:20 2005
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*
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* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/mmu_defs_asm.h ../../inst/mmu/doc/mmu_regs.r
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* id: $Id: mmu_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
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* Any changes here will be lost.
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*
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* -*- buffer-read-only: t -*-
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*/
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#ifndef REG_FIELD
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#define REG_FIELD( scope, reg, field, value ) \
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REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
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#define REG_FIELD_X_( value, shift ) ((value) << shift)
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#endif
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#ifndef REG_STATE
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#define REG_STATE( scope, reg, field, symbolic_value ) \
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REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
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#define REG_STATE_X_( k, shift ) (k << shift)
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#endif
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#ifndef REG_MASK
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#define REG_MASK( scope, reg, field ) \
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REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
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#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
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#endif
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#ifndef REG_LSB
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#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
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#endif
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#ifndef REG_BIT
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#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
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#endif
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#ifndef REG_ADDR
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#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
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#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
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#endif
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#ifndef REG_ADDR_VECT
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#define REG_ADDR_VECT( scope, inst, reg, index ) \
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REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
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STRIDE_##scope##_##reg )
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#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
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((inst) + offs + (index) * stride)
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#endif
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/* Register rw_mm_cfg, scope mmu, type rw */
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#define reg_mmu_rw_mm_cfg___seg_0___lsb 0
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#define reg_mmu_rw_mm_cfg___seg_0___width 1
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#define reg_mmu_rw_mm_cfg___seg_0___bit 0
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#define reg_mmu_rw_mm_cfg___seg_1___lsb 1
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#define reg_mmu_rw_mm_cfg___seg_1___width 1
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#define reg_mmu_rw_mm_cfg___seg_1___bit 1
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#define reg_mmu_rw_mm_cfg___seg_2___lsb 2
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#define reg_mmu_rw_mm_cfg___seg_2___width 1
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#define reg_mmu_rw_mm_cfg___seg_2___bit 2
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#define reg_mmu_rw_mm_cfg___seg_3___lsb 3
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#define reg_mmu_rw_mm_cfg___seg_3___width 1
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#define reg_mmu_rw_mm_cfg___seg_3___bit 3
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#define reg_mmu_rw_mm_cfg___seg_4___lsb 4
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#define reg_mmu_rw_mm_cfg___seg_4___width 1
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#define reg_mmu_rw_mm_cfg___seg_4___bit 4
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#define reg_mmu_rw_mm_cfg___seg_5___lsb 5
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#define reg_mmu_rw_mm_cfg___seg_5___width 1
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#define reg_mmu_rw_mm_cfg___seg_5___bit 5
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#define reg_mmu_rw_mm_cfg___seg_6___lsb 6
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#define reg_mmu_rw_mm_cfg___seg_6___width 1
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#define reg_mmu_rw_mm_cfg___seg_6___bit 6
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#define reg_mmu_rw_mm_cfg___seg_7___lsb 7
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#define reg_mmu_rw_mm_cfg___seg_7___width 1
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#define reg_mmu_rw_mm_cfg___seg_7___bit 7
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#define reg_mmu_rw_mm_cfg___seg_8___lsb 8
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#define reg_mmu_rw_mm_cfg___seg_8___width 1
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#define reg_mmu_rw_mm_cfg___seg_8___bit 8
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#define reg_mmu_rw_mm_cfg___seg_9___lsb 9
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#define reg_mmu_rw_mm_cfg___seg_9___width 1
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#define reg_mmu_rw_mm_cfg___seg_9___bit 9
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#define reg_mmu_rw_mm_cfg___seg_a___lsb 10
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#define reg_mmu_rw_mm_cfg___seg_a___width 1
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#define reg_mmu_rw_mm_cfg___seg_a___bit 10
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#define reg_mmu_rw_mm_cfg___seg_b___lsb 11
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#define reg_mmu_rw_mm_cfg___seg_b___width 1
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#define reg_mmu_rw_mm_cfg___seg_b___bit 11
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#define reg_mmu_rw_mm_cfg___seg_c___lsb 12
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#define reg_mmu_rw_mm_cfg___seg_c___width 1
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#define reg_mmu_rw_mm_cfg___seg_c___bit 12
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#define reg_mmu_rw_mm_cfg___seg_d___lsb 13
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#define reg_mmu_rw_mm_cfg___seg_d___width 1
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#define reg_mmu_rw_mm_cfg___seg_d___bit 13
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#define reg_mmu_rw_mm_cfg___seg_e___lsb 14
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#define reg_mmu_rw_mm_cfg___seg_e___width 1
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#define reg_mmu_rw_mm_cfg___seg_e___bit 14
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#define reg_mmu_rw_mm_cfg___seg_f___lsb 15
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#define reg_mmu_rw_mm_cfg___seg_f___width 1
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#define reg_mmu_rw_mm_cfg___seg_f___bit 15
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#define reg_mmu_rw_mm_cfg___inv___lsb 16
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#define reg_mmu_rw_mm_cfg___inv___width 1
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#define reg_mmu_rw_mm_cfg___inv___bit 16
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#define reg_mmu_rw_mm_cfg___ex___lsb 17
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#define reg_mmu_rw_mm_cfg___ex___width 1
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#define reg_mmu_rw_mm_cfg___ex___bit 17
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#define reg_mmu_rw_mm_cfg___acc___lsb 18
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#define reg_mmu_rw_mm_cfg___acc___width 1
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#define reg_mmu_rw_mm_cfg___acc___bit 18
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#define reg_mmu_rw_mm_cfg___we___lsb 19
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#define reg_mmu_rw_mm_cfg___we___width 1
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#define reg_mmu_rw_mm_cfg___we___bit 19
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#define reg_mmu_rw_mm_cfg_offset 0
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/* Register rw_mm_kbase_lo, scope mmu, type rw */
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#define reg_mmu_rw_mm_kbase_lo___base_0___lsb 0
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#define reg_mmu_rw_mm_kbase_lo___base_0___width 4
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#define reg_mmu_rw_mm_kbase_lo___base_1___lsb 4
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#define reg_mmu_rw_mm_kbase_lo___base_1___width 4
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#define reg_mmu_rw_mm_kbase_lo___base_2___lsb 8
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#define reg_mmu_rw_mm_kbase_lo___base_2___width 4
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#define reg_mmu_rw_mm_kbase_lo___base_3___lsb 12
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#define reg_mmu_rw_mm_kbase_lo___base_3___width 4
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#define reg_mmu_rw_mm_kbase_lo___base_4___lsb 16
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#define reg_mmu_rw_mm_kbase_lo___base_4___width 4
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#define reg_mmu_rw_mm_kbase_lo___base_5___lsb 20
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#define reg_mmu_rw_mm_kbase_lo___base_5___width 4
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#define reg_mmu_rw_mm_kbase_lo___base_6___lsb 24
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#define reg_mmu_rw_mm_kbase_lo___base_6___width 4
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#define reg_mmu_rw_mm_kbase_lo___base_7___lsb 28
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#define reg_mmu_rw_mm_kbase_lo___base_7___width 4
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#define reg_mmu_rw_mm_kbase_lo_offset 4
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/* Register rw_mm_kbase_hi, scope mmu, type rw */
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#define reg_mmu_rw_mm_kbase_hi___base_8___lsb 0
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#define reg_mmu_rw_mm_kbase_hi___base_8___width 4
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#define reg_mmu_rw_mm_kbase_hi___base_9___lsb 4
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#define reg_mmu_rw_mm_kbase_hi___base_9___width 4
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#define reg_mmu_rw_mm_kbase_hi___base_a___lsb 8
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#define reg_mmu_rw_mm_kbase_hi___base_a___width 4
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#define reg_mmu_rw_mm_kbase_hi___base_b___lsb 12
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#define reg_mmu_rw_mm_kbase_hi___base_b___width 4
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#define reg_mmu_rw_mm_kbase_hi___base_c___lsb 16
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#define reg_mmu_rw_mm_kbase_hi___base_c___width 4
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#define reg_mmu_rw_mm_kbase_hi___base_d___lsb 20
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#define reg_mmu_rw_mm_kbase_hi___base_d___width 4
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#define reg_mmu_rw_mm_kbase_hi___base_e___lsb 24
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#define reg_mmu_rw_mm_kbase_hi___base_e___width 4
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#define reg_mmu_rw_mm_kbase_hi___base_f___lsb 28
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#define reg_mmu_rw_mm_kbase_hi___base_f___width 4
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#define reg_mmu_rw_mm_kbase_hi_offset 8
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/* Register r_mm_cause, scope mmu, type r */
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#define reg_mmu_r_mm_cause___pid___lsb 0
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#define reg_mmu_r_mm_cause___pid___width 8
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#define reg_mmu_r_mm_cause___op___lsb 8
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#define reg_mmu_r_mm_cause___op___width 2
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#define reg_mmu_r_mm_cause___vpn___lsb 13
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#define reg_mmu_r_mm_cause___vpn___width 19
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#define reg_mmu_r_mm_cause_offset 12
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/* Register rw_mm_tlb_sel, scope mmu, type rw */
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#define reg_mmu_rw_mm_tlb_sel___idx___lsb 0
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#define reg_mmu_rw_mm_tlb_sel___idx___width 4
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#define reg_mmu_rw_mm_tlb_sel___set___lsb 4
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#define reg_mmu_rw_mm_tlb_sel___set___width 2
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#define reg_mmu_rw_mm_tlb_sel_offset 16
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/* Register rw_mm_tlb_lo, scope mmu, type rw */
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#define reg_mmu_rw_mm_tlb_lo___x___lsb 0
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#define reg_mmu_rw_mm_tlb_lo___x___width 1
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#define reg_mmu_rw_mm_tlb_lo___x___bit 0
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#define reg_mmu_rw_mm_tlb_lo___w___lsb 1
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#define reg_mmu_rw_mm_tlb_lo___w___width 1
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#define reg_mmu_rw_mm_tlb_lo___w___bit 1
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#define reg_mmu_rw_mm_tlb_lo___k___lsb 2
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#define reg_mmu_rw_mm_tlb_lo___k___width 1
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#define reg_mmu_rw_mm_tlb_lo___k___bit 2
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#define reg_mmu_rw_mm_tlb_lo___v___lsb 3
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#define reg_mmu_rw_mm_tlb_lo___v___width 1
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#define reg_mmu_rw_mm_tlb_lo___v___bit 3
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#define reg_mmu_rw_mm_tlb_lo___g___lsb 4
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#define reg_mmu_rw_mm_tlb_lo___g___width 1
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#define reg_mmu_rw_mm_tlb_lo___g___bit 4
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#define reg_mmu_rw_mm_tlb_lo___pfn___lsb 13
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#define reg_mmu_rw_mm_tlb_lo___pfn___width 19
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#define reg_mmu_rw_mm_tlb_lo_offset 20
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/* Register rw_mm_tlb_hi, scope mmu, type rw */
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#define reg_mmu_rw_mm_tlb_hi___pid___lsb 0
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#define reg_mmu_rw_mm_tlb_hi___pid___width 8
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#define reg_mmu_rw_mm_tlb_hi___vpn___lsb 13
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#define reg_mmu_rw_mm_tlb_hi___vpn___width 19
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#define reg_mmu_rw_mm_tlb_hi_offset 24
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/* Constants */
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#define regk_mmu_execute 0x00000000
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#define regk_mmu_flush 0x00000003
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#define regk_mmu_linear 0x00000001
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#define regk_mmu_no 0x00000000
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#define regk_mmu_off 0x00000000
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#define regk_mmu_on 0x00000001
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#define regk_mmu_page 0x00000000
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#define regk_mmu_read 0x00000001
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#define regk_mmu_write 0x00000002
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#define regk_mmu_yes 0x00000001
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#endif /* __mmu_defs_asm_h */
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