230 lines
8.7 KiB
C
230 lines
8.7 KiB
C
#ifndef __timer_defs_asm_h
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#define __timer_defs_asm_h
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/*
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* This file is autogenerated from
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* file: ../../inst/timer/rtl/timer_regs.r
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* id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
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* last modfied: Mon Apr 11 16:09:53 2005
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*
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* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r
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* id: $Id: timer_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
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* Any changes here will be lost.
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*
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* -*- buffer-read-only: t -*-
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*/
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#ifndef REG_FIELD
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#define REG_FIELD( scope, reg, field, value ) \
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REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
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#define REG_FIELD_X_( value, shift ) ((value) << shift)
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#endif
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#ifndef REG_STATE
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#define REG_STATE( scope, reg, field, symbolic_value ) \
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REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
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#define REG_STATE_X_( k, shift ) (k << shift)
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#endif
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#ifndef REG_MASK
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#define REG_MASK( scope, reg, field ) \
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REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
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#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
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#endif
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#ifndef REG_LSB
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#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
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#endif
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#ifndef REG_BIT
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#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
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#endif
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#ifndef REG_ADDR
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#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
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#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
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#endif
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#ifndef REG_ADDR_VECT
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#define REG_ADDR_VECT( scope, inst, reg, index ) \
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REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
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STRIDE_##scope##_##reg )
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#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
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((inst) + offs + (index) * stride)
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#endif
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/* Register rw_tmr0_div, scope timer, type rw */
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#define reg_timer_rw_tmr0_div_offset 0
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/* Register r_tmr0_data, scope timer, type r */
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#define reg_timer_r_tmr0_data_offset 4
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/* Register rw_tmr0_ctrl, scope timer, type rw */
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#define reg_timer_rw_tmr0_ctrl___op___lsb 0
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#define reg_timer_rw_tmr0_ctrl___op___width 2
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#define reg_timer_rw_tmr0_ctrl___freq___lsb 2
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#define reg_timer_rw_tmr0_ctrl___freq___width 3
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#define reg_timer_rw_tmr0_ctrl_offset 8
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/* Register rw_tmr1_div, scope timer, type rw */
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#define reg_timer_rw_tmr1_div_offset 16
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/* Register r_tmr1_data, scope timer, type r */
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#define reg_timer_r_tmr1_data_offset 20
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/* Register rw_tmr1_ctrl, scope timer, type rw */
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#define reg_timer_rw_tmr1_ctrl___op___lsb 0
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#define reg_timer_rw_tmr1_ctrl___op___width 2
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#define reg_timer_rw_tmr1_ctrl___freq___lsb 2
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#define reg_timer_rw_tmr1_ctrl___freq___width 3
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#define reg_timer_rw_tmr1_ctrl_offset 24
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/* Register rs_cnt_data, scope timer, type rs */
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#define reg_timer_rs_cnt_data___tmr___lsb 0
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#define reg_timer_rs_cnt_data___tmr___width 24
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#define reg_timer_rs_cnt_data___cnt___lsb 24
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#define reg_timer_rs_cnt_data___cnt___width 8
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#define reg_timer_rs_cnt_data_offset 32
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/* Register r_cnt_data, scope timer, type r */
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#define reg_timer_r_cnt_data___tmr___lsb 0
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#define reg_timer_r_cnt_data___tmr___width 24
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#define reg_timer_r_cnt_data___cnt___lsb 24
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#define reg_timer_r_cnt_data___cnt___width 8
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#define reg_timer_r_cnt_data_offset 36
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/* Register rw_cnt_cfg, scope timer, type rw */
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#define reg_timer_rw_cnt_cfg___clk___lsb 0
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#define reg_timer_rw_cnt_cfg___clk___width 2
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#define reg_timer_rw_cnt_cfg_offset 40
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/* Register rw_trig, scope timer, type rw */
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#define reg_timer_rw_trig_offset 48
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/* Register rw_trig_cfg, scope timer, type rw */
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#define reg_timer_rw_trig_cfg___tmr___lsb 0
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#define reg_timer_rw_trig_cfg___tmr___width 2
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#define reg_timer_rw_trig_cfg_offset 52
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/* Register r_time, scope timer, type r */
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#define reg_timer_r_time_offset 56
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/* Register rw_out, scope timer, type rw */
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#define reg_timer_rw_out___tmr___lsb 0
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#define reg_timer_rw_out___tmr___width 2
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#define reg_timer_rw_out_offset 60
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/* Register rw_wd_ctrl, scope timer, type rw */
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#define reg_timer_rw_wd_ctrl___cnt___lsb 0
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#define reg_timer_rw_wd_ctrl___cnt___width 8
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#define reg_timer_rw_wd_ctrl___cmd___lsb 8
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#define reg_timer_rw_wd_ctrl___cmd___width 1
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#define reg_timer_rw_wd_ctrl___cmd___bit 8
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#define reg_timer_rw_wd_ctrl___key___lsb 9
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#define reg_timer_rw_wd_ctrl___key___width 7
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#define reg_timer_rw_wd_ctrl_offset 64
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/* Register r_wd_stat, scope timer, type r */
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#define reg_timer_r_wd_stat___cnt___lsb 0
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#define reg_timer_r_wd_stat___cnt___width 8
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#define reg_timer_r_wd_stat___cmd___lsb 8
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#define reg_timer_r_wd_stat___cmd___width 1
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#define reg_timer_r_wd_stat___cmd___bit 8
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#define reg_timer_r_wd_stat_offset 68
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/* Register rw_intr_mask, scope timer, type rw */
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#define reg_timer_rw_intr_mask___tmr0___lsb 0
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#define reg_timer_rw_intr_mask___tmr0___width 1
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#define reg_timer_rw_intr_mask___tmr0___bit 0
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#define reg_timer_rw_intr_mask___tmr1___lsb 1
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#define reg_timer_rw_intr_mask___tmr1___width 1
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#define reg_timer_rw_intr_mask___tmr1___bit 1
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#define reg_timer_rw_intr_mask___cnt___lsb 2
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#define reg_timer_rw_intr_mask___cnt___width 1
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#define reg_timer_rw_intr_mask___cnt___bit 2
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#define reg_timer_rw_intr_mask___trig___lsb 3
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#define reg_timer_rw_intr_mask___trig___width 1
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#define reg_timer_rw_intr_mask___trig___bit 3
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#define reg_timer_rw_intr_mask_offset 72
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/* Register rw_ack_intr, scope timer, type rw */
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#define reg_timer_rw_ack_intr___tmr0___lsb 0
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#define reg_timer_rw_ack_intr___tmr0___width 1
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#define reg_timer_rw_ack_intr___tmr0___bit 0
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#define reg_timer_rw_ack_intr___tmr1___lsb 1
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#define reg_timer_rw_ack_intr___tmr1___width 1
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#define reg_timer_rw_ack_intr___tmr1___bit 1
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#define reg_timer_rw_ack_intr___cnt___lsb 2
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#define reg_timer_rw_ack_intr___cnt___width 1
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#define reg_timer_rw_ack_intr___cnt___bit 2
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#define reg_timer_rw_ack_intr___trig___lsb 3
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#define reg_timer_rw_ack_intr___trig___width 1
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#define reg_timer_rw_ack_intr___trig___bit 3
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#define reg_timer_rw_ack_intr_offset 76
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/* Register r_intr, scope timer, type r */
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#define reg_timer_r_intr___tmr0___lsb 0
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#define reg_timer_r_intr___tmr0___width 1
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#define reg_timer_r_intr___tmr0___bit 0
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#define reg_timer_r_intr___tmr1___lsb 1
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#define reg_timer_r_intr___tmr1___width 1
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#define reg_timer_r_intr___tmr1___bit 1
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#define reg_timer_r_intr___cnt___lsb 2
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#define reg_timer_r_intr___cnt___width 1
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#define reg_timer_r_intr___cnt___bit 2
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#define reg_timer_r_intr___trig___lsb 3
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#define reg_timer_r_intr___trig___width 1
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#define reg_timer_r_intr___trig___bit 3
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#define reg_timer_r_intr_offset 80
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/* Register r_masked_intr, scope timer, type r */
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#define reg_timer_r_masked_intr___tmr0___lsb 0
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#define reg_timer_r_masked_intr___tmr0___width 1
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#define reg_timer_r_masked_intr___tmr0___bit 0
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#define reg_timer_r_masked_intr___tmr1___lsb 1
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#define reg_timer_r_masked_intr___tmr1___width 1
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#define reg_timer_r_masked_intr___tmr1___bit 1
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#define reg_timer_r_masked_intr___cnt___lsb 2
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#define reg_timer_r_masked_intr___cnt___width 1
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#define reg_timer_r_masked_intr___cnt___bit 2
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#define reg_timer_r_masked_intr___trig___lsb 3
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#define reg_timer_r_masked_intr___trig___width 1
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#define reg_timer_r_masked_intr___trig___bit 3
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#define reg_timer_r_masked_intr_offset 84
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/* Register rw_test, scope timer, type rw */
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#define reg_timer_rw_test___dis___lsb 0
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#define reg_timer_rw_test___dis___width 1
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#define reg_timer_rw_test___dis___bit 0
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#define reg_timer_rw_test___en___lsb 1
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#define reg_timer_rw_test___en___width 1
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#define reg_timer_rw_test___en___bit 1
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#define reg_timer_rw_test_offset 88
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/* Constants */
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#define regk_timer_ext 0x00000001
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#define regk_timer_f100 0x00000007
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#define regk_timer_f29_493 0x00000004
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#define regk_timer_f32 0x00000005
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#define regk_timer_f32_768 0x00000006
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#define regk_timer_hold 0x00000001
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#define regk_timer_ld 0x00000000
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#define regk_timer_no 0x00000000
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#define regk_timer_off 0x00000000
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#define regk_timer_run 0x00000002
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#define regk_timer_rw_cnt_cfg_default 0x00000000
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#define regk_timer_rw_intr_mask_default 0x00000000
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#define regk_timer_rw_out_default 0x00000000
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#define regk_timer_rw_test_default 0x00000000
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#define regk_timer_rw_tmr0_ctrl_default 0x00000000
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#define regk_timer_rw_tmr1_ctrl_default 0x00000000
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#define regk_timer_rw_trig_cfg_default 0x00000000
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#define regk_timer_start 0x00000001
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#define regk_timer_stop 0x00000000
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#define regk_timer_time 0x00000001
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#define regk_timer_tmr0 0x00000002
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#define regk_timer_tmr1 0x00000003
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#define regk_timer_yes 0x00000001
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#endif /* __timer_defs_asm_h */
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